DSPIC33FJ64GP306 Microchip Technology Inc., DSPIC33FJ64GP306 Datasheet - Page 316

• Manufacturer Part Number: DSPIC33FJ64GP306
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10
DCI I/O Pins ...................................................................... 217
DCI Module
Development Support ....................................................... 261
Differences Between "PS" and Final Production
DMA Module
DMAC Registers ............................................................... 126
DSP Engine......................................................................... 23
E
ECAN Module
Electrical Characteristics................................................... 265
Enhanced CAN Module..................................................... 187
Equations
Errata .................................................................................. 12
DS70286A-page 312
Slot Enable Bits Operation with Frame Sync ............ 222
Slot Status Bits.......................................................... 224
Synchronous Data Transfers .................................... 222
Transmit Slot Enable Bits.......................................... 222
Transmit Status Bits .................................................. 223
Transmit/Receive Shift Register ............................... 217
Underflow Mode Control Bit ...................................... 224
Word Size Selection Bits........................................... 219
COFS ........................................................................ 217
CSCK ........................................................................ 217
CSDI ......................................................................... 217
CSDO........................................................................ 217
Register Map............................................................... 54
Devices ..................................................................... 309
DMA Register Map...................................................... 46
DMAxCNT ................................................................. 126
DMAxCON ................................................................ 126
DMAxPAD ................................................................. 126
DMAxREQ ................................................................ 126
DMAxSTA ................................................................. 126
DMAxSTB ................................................................. 126
Multiplier...................................................................... 25
Baud Rate Setting..................................................... 192
ECAN1 Register Map (C1CTRL1.WIN = 0 or 1) ......... 48
ECAN1 Register Map (C1CTRL1.WIN = 0) ................ 48
ECAN1 Register Map (C1CTRL1.WIN = 1) ................ 49
ECAN2 Register Map (C2CTRL1.WIN = 0 or 1) ......... 51
ECAN2 Register Map (C2CTRL1.WIN = 0) .......... 51, 52
Frame Types ............................................................. 187
Message Reception .................................................. 189
Message Transmission ............................................. 191
Modes of Operation .................................................. 189
Overview ................................................................... 187
AC ............................................................................. 273
A/D Conversion Clock Period ................................... 234
Bit Clock Frequency .................................................. 221
Calculating the PWM Period ..................................... 158
Calculation for Maximum PWM Resolution............... 158
COFSG Period .......................................................... 219
Device Operating Frequency .................................... 136
Relationship Between Device and SPI
Serial Clock Rate ...................................................... 169
Time Quantum for Clock Generation ........................ 193
UART Baud Rate with BRGH = 0 ............................. 180
UART Baud Rate with BRGH = 1 ............................. 180
Clock Speed...................................................... 164
F
Flash Program Memory ...................................................... 67
Flexible Configuration ....................................................... 245
FSCM
I
I/O Ports............................................................................ 145
I
I
I
In-Circuit Debugger........................................................... 251
In-Circuit Emulation .......................................................... 245
In-Circuit Serial Programming (ICSP)....................... 245, 251
Infrared Support
Input Capture
Input Change Notification Module..................................... 146
Instruction Addressing Modes ............................................ 57
Instruction Set
Instruction-Based Power-Saving Modes........................... 143
Internal RC Oscillator
Internet Address ............................................................... 317
2
2
2
C
C Module
S Mode Operation .......................................................... 225
Control Registers ........................................................ 68
Operations .................................................................. 68
Programming Algorithm .............................................. 71
RTSP Operation ......................................................... 68
Table Instructions ....................................................... 67
Delay for Crystal and PLL Clock Sources................... 77
Device Resets............................................................. 77
Parallel I/O (PIO) ...................................................... 145
Write/Read Timing .................................................... 146
Addresses................................................................. 171
Baud Rate Generator ............................................... 169
General Call Address Support .................................. 171
Interrupts .................................................................. 169
IPMI Support............................................................. 171
Master Mode Operation
Operating Modes ...................................................... 169
Registers .................................................................. 169
Slave Address Masking ............................................ 171
Slope Control ............................................................ 172
Software Controlled Clock Stretching (STREN = 1) . 171
I2C1 Register Map...................................................... 43
I2C2 Register Map...................................................... 43
Data Justification ...................................................... 225
Frame and Data Word Length Selection .................. 225
Built-in IrDA Encoder and Decoder........................... 181
External IrDA, IrDA Clock Output ............................. 181
Registers .................................................................. 156
File Register Instructions ............................................ 57
Fundamental Modes Supported ................................. 58
MAC Instructions ........................................................ 58
MCU Instructions ........................................................ 57
Move and Accumulator Instructions............................ 58
Other Instructions ....................................................... 58
Overview................................................................... 256
Summary .................................................................. 253
Idle ............................................................................ 144
Sleep ........................................................................ 143
Use with WDT........................................................... 250
Clock Arbitration ............................................... 172
Multi-Master Communication, Bus Collision
and Bus Arbitration ................................... 172
© 2007 Microchip Technology Inc.