PDU53 Data Delay Devices, Inc., PDU53 Datasheet
PDU53
Related parts for PDU53
PDU53 Summary of contents
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... Input & outputs fully 100K-ECL interfaced & buffered • Available in 16-pin DIP (600 mil) socket or SMD FUNCTIONAL DESCRIPTION The PDU53-series device is a 3-bit digitally programmable delay line. The delay from the input pin (IN) to the output pin (OUT) depends on the A address code (A2-A0) according to the following formula: ...
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... PDU53 ADDRESS UPDATE The PDU53 is a memory device. As such, special precautions must be taken when changing the delay address in order to prevent spurious output signals. The timing restrictions are shown in Figure 1. After the last signal edge to be delayed has appeared on the OUT pin, a minimum time required before the address lines can change ...
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... PACKAGE DIMENSIONS (cont’d) .020 TYP .090 .880±.020 PDU53-xxC3 PDU53-xxMC3 (Military SMD) DEVICE SPECIFICATIONS TABLE 1: AC CHARACTERISTICS PARAMETER Total Programmable Delay Inherent Delay Address to Input Setup Time Output to Address Change Input Period Recommended Input Pulse Width ...
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... PDU53 DELAY LINE AUTOMATED TESTING INPUT ± 3 Ambient Temperature: 25 Supply Voltage (Vcc): -4.5V ± 0.1V Input Pulse: Standard 100K ECL levels Source Impedance: 50Ω Max. Rise/Fall Time: 1.0 ns Max. (measured between 20% and 80%) Pulse Width 10ns IN Period: PER = 100ns IN NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. ...