HMP41GF7MMP8C Hynix Semiconductor, HMP41GF7MMP8C Datasheet
HMP41GF7MMP8C
Related parts for HMP41GF7MMP8C
HMP41GF7MMP8C Summary of contents
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... Full DIMM Heat Spreader ORDERING INFORMATION Part Name Density HMP41GF7MMP8C-C4xx/Y5xx Note FDHS means Full DIMM Heat Spreader. This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. ...
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AMB INFORMATION ID Manufacturer D3 IDT N3 INTEL SPEED GRADE & KEY PARAMETERS Speed Grade DDR2 DRAM Speed Grade FB-DIMM Speed Grade FB-DIMM Peak Channel Throughput FB-DIMM Link Transfer Rate ADDRESS TABLE Density Organization Ranks 8GB Supply ...
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Input/Output Functional Description Pin Name type Polarity SCK Input SCK Input Negative PN[13:0] Output PN[13:0] Output Negative PS[9:0] Input PS[9:0] Input Negative SN[13:0] Output SN[13:0] Output Negative SS[9:0] Input SS[9:0] Input Negative SCL Input SDA Input / Output SA[2:0] Input ...
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PIN ASSIGNMENT Pin Name Pin Name 1 VDD 41 PN13 2 VDD 42 VSS 3 VDD 43 VSS 4 VSS 44 RFU* 5 VDD 45 RFU* 6 VDD 46 VSS 7 VDD 47 VSS 8 VSS 48 PN12 9 VCC ...
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FUNCTIONAL BLOCK DIAGRAM 8GB(1Gbx72) ECC FB-DIMM : HMP41GF7MMP4C VSS /S1 /S0 /DQS0 DQS0 DQS /DQS /CS DM DQ0 I/O 0 DQ1 I I/O 2 DQ2 DQ3 I/O 3 /DQS1 DQS1 DM DQS /DQS / I/O 0 ...
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Architecture Advanced Memory Buffer Pin Description Pin Namel SCK System Clock Input, positive line SCK System Clock Input, negative line PN[13:0] Primary Northbound Data, positive lines PN[13:0] Primary Northbound Data, negative lines PS[9:0] Primary Southbound Data, positive lines PS[9:0] Primary ...
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Advanced Memory Buffer Pin Description Pin Namel SCL Serial Presence Detect (SPD) Clock Input SDA SPD Data Input / Output SA{2:0] SPD Address Inputs, also used to select the DIMM number in the AMB PLLTSTO PLL Clock Observability Output VCCAPLL ...
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Pin Assignments for the Advanced Memory Buffer(AMB) (Top View) 655-Ball LFBGA 0 0.8 mm pitch Left Side VSS DQ26 DQ12 B VDD DQS3 DQS3 C VSS DQS2 DQ18 VSS D DQ19 DQS2 VSS ...
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Right Side VDD TEST VDD DQ52 B VDD TEST DDRC C DQS17 VSS DDRC DQ54 D CB6 CB7 VSS DQS16 E VSS CB5 DQS16 F CB4 VDD DQ62 DQ60 G TESTLO RFU RFU H VSS VDD ...
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Advanced Memory Buffer(AMB) DRAM Interface Specifications Plsease refer to the AMB Specification for all technical requirements The following specifications for the AMB constitute the subset which is critical for proper operation of the DDR2 SDRAM interface. Note: This list is ...
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Basic Functionality 1. Advanced Memory Buffer Overview The Advanced Memory Buffer refernce design complies with the JEDEC FB-DIMM Archtecture and Protocol Specification. 2. Advanced Memory Buffer Functionality 2.1 Advanced Memory Buffer • Supports channel initialization procedures ans defined in the ...
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Advanced Memory Buffer Block Diagram North PLL 1x2 Reset# Reset Control Command Decoder & CRC Check Thermal Sensor Core Control & CSRs LAI Controller SMbus SMbus Controller Northbound DataOut Advanced Memory Buffer Block Diagram Rev 0.1 / May 2008 ...
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Interfaces Below Figure illustrates the AMB and all of its interfaces.They consits of two FB-DIMM links, one DDR2 channel and an SMBus interface. Each FB-DIMM link connects the AMB to a host meory controller or an adjacent FB-DIMM. Ther ...
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SMBus Slave Interface The Advanced Memory Buffer supports an SMBus interface to allow system access to configuration regis- ters independent of the FB-DIMM link. The Advanced Memory Buffer will never be a master on the SMBus, only a slave. ...
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Hot-add The FB-DIMM channel does not provide a mechanism to automatically detect and report the addition of a new DIMM south of the currently active last DIMM assumed the system will be notified through some means of ...
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Electrical Characteristics ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pins relative to Vss Voltage on V relative to Vss CC Voltage on V relative to Vss DD Voltage on V relative to Vss TT Storage Temperature range Note : 1. ...
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Timing Parameters Parameter EI Assertion Pass-Thru Timing EI Deassertion Pass-Thru Timing EI Assertion Duration Bit Lock Interval Frame Lock Interval Note: 1. Defined in FB-DIMM Architecture and Protocol Spec. Environmental Parameters Symbol T Operating temperature OPR H Operating humidity(relative) OPR ...
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IDD Specification and Conditions I Meauarement Conditions DD Symbol Idle_0 Idle_1 Idle_2 Active_1 Active_2 L0s Training (for AMB spec, not in SPD) Rev 0.1 / May 2008 240pin Fully Buffered DDR2 SDRAM DIMMs 1 Idle Current, single or last DIMML0 ...
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IDD Power Supply Currents Specifications. SAC Timing Parameters by Speed Grade Power Supply Icc_Idle_0 @1.5V Idd_Idle_0 @1.8V Idle_0 Total Power Icc_Idle_1 @1.5V Idd_Idle_1 @1.8V Idle_1 Total Power Icc_Idle_2 @1.5V Idd_Idle_2 @1.8V Idle_2 Total Power Icc_Active_1 @1.5V Idd_Active_1 @1.8V Active_1 Total ...
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Termination Current Internal signals are terminated on the DIMM throughresistors to an external power supply VTT = VDD / 2.Modeled with 30 Ohm termination for clocks, 39 ohmfor command / address and 47 ohm for control. TheVTT power supply must ...
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PACKAGE OUTLINE 1Gbx72 (2 rank) - HMP41GF7MMP4C D1/D19 D2/D20 D0/D18 67.00 D10 D11 D9/D27 /D28 /D29 FRONT VIEW WITH HEAT SPREADER BACK VIEW WITH HEAT SPREADER Note 1: All dimensions are typical millimeter scale unless otherwise stated. Rev 0.1 / ...
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REVISION HISTORY Revision 0.1 First Version Release Rev 0.1 / May 2008 240pin Fully Buffered DDR2 SDRAM DIMMs 1 History Date Remark May 2008 22 ...