ADRF6750 Analog Devices, Inc., ADRF6750 Datasheet - Page 22

• Manufacturer Part Number: ADRF6750
• Description: 950 Mhz To 1575 Mhz Quadrature Modulator With Integrated Fractional-n Pll And Vco
• Manufacturer: Analog Devices, Inc.

ADRF6750
clock (SCL) inputs carry information between any devices that
are connected to the bus. Each slave device is recognized by
a unique address. The ADRF6750 has two possible 7-bit slave
addresses for both read and write operations. The MSB of the
7-bit slave address is set to 1. Bit 5 of the slave address is set by
the CS pin (Pin 27). Bits[4:0] of the slave address are set to all
0s. The slave address consists of the seven MSBs of an 8-bit
word. The LSB of the word sets either a read or a write oper-
ation (see Figure 63). Logic 1 corresponds to a read operation,
whereas Logic 0 corresponds to a write operation.
To control the device on the bus, the following protocol must
be followed. The master initiates a data transfer by establishing
a start condition, defined by a high-to-low transition on SDA
while SCL remains high. This indicates that an address/data
stream follows. All peripherals respond to the start condition
and shift the next eight bits (the 7-bit address and the R/W bit).
The bits are transferred from MSB to LSB. The peripheral that
recognizes the transmitted address responds by pulling the data
line low during the ninth clock pulse. This is known as an
acknowledge bit. All other devices then withdraw from the bus
and maintain an idle condition. During the idle condition, the
device monitors the SDA and SCL lines waiting for the start
condition and the correct transmitted address. The R/W bit
determines the direction of the data. Logic 0 on the LSB of the
SDA
SCL
START BIT
S
S = START BIT
A(S) = ACKNOWLEDGE BY SLAVE
S
A6
SLAVE ADDR, LSB = 0 (WR)
SLAVE ADDRESS
A5
S = START BIT
A(S) = ACKNOWLEDGE BY SLAVE
S
ADDR[4:0]
SLAVE
SLAVE ADDR, LSB = 0 (WR) A(S)
MSB = 1 SET BY
1
A(S)
SLAVE ADDRESS[6:0]
PIN 27
SUBADDR
(CS)
A5
WR
Figure 63. Slave Address Configuration
Figure 66. I
Figure 64. I
P = STOP BIT
A(M) = ACKNOWLEDGE BY MASTER
Figure 65. I
0
ACK
A(S)
Rev. 0 | Page 22 of 40
SUBADDR
SUBADDRESS
S
2
P = STOP BIT
2
C Data Transfer Timing
2
0
C Write Data Transfer
C Read Data Transfer
A7
SLAVE ADDR, LSB = 1 (RD)
SUBADDR[6:1]
0
A(S)
first byte indicates that the master writes information to the
peripheral. Logic 1 on the LSB of the first byte indicates that the
master reads information from the peripheral.
The ADRF6750 acts as a standard slave device on the bus. The
data on the SDA pin (Pin 29) is eight bits long, supporting the
7-bit addresses plus the R/W bit. The ADRF6750 has 34 subad-
dresses to enable the user-accessible internal registers. Therefore,
it interprets the first byte as the device address and the second
byte as the starting subaddress. Autoincrement mode is supported,
which allows data to be read from or written to the starting sub-
address and each subsequent address without manually addressing
the subsequent subaddress. A data transfer is always terminated
by a stop condition. The user can also access any unique subaddress
register on a one-by-one basis without updating all registers.
Stop and start conditions can be detected at any stage of the data
transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate jump
to the idle condition. If an invalid subaddress is issued by the
user, the ADRF6750 does not issue an acknowledge and returns
to the idle condition. In a no acknowledge condition, the SDA
line is not pulled low on the ninth pulse. See Figure 64 and
Figure 65 for sample write and read data transfers, Figure 66 for
the timing protocol, and Figure 2 for a more detailed timing
diagram.
DATA
0
A0
A(S)
A(M) = NO ACKNOWLEDGE BY MASTER
0
A(S) DATA A(M)
ACK
0 = WR
1 = RD
R/W
CTRL
DATA
X
D7
DATA
A(S)
DATA[6:1]
P
DATA
A(M)
D0
P
ACK
STOP BIT
P