ADRF6750 Analog Devices, Inc., ADRF6750 Datasheet - Page 31

• Manufacturer Part Number: ADRF6750
• Description: 950 Mhz To 1575 Mhz Quadrature Modulator With Integrated Fractional-n Pll And Vco
• Manufacturer: Analog Devices, Inc.

SUGGESTED POWER-UP SEQUENCE
INITIAL REGISTER WRITE SEQUENCE
After applying power to the part, perform the initial register write
sequence that follows. Note that Register CR33, Register CR32,
and Register CR31 are read-only registers. Also note that all writ-
able registers should be written to on power-up. Refer to the
Register Map section for more details on all registers.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Write Register CR21: 0x00. Reserved register.
11. Write Register CR20: 0x00. Reserved register.
12. Write Register CR19: 0x00. Reserved register.
13. Write Register CR18: 0x00. Reserved register.
14. Write Register CR17: 0x00. Reserved register.
15. Write Register CR16: 0x00. Reserved register.
16. Write Register CR15: 0x00. Reserved register.
17. Write Register CR14: 0x1B. The attenuator is always
18. Write Register CR13: 0x18. Reserved register.
19. Write Register CR12: 0x08. PLL powered up.
20. Write Register CR11: 0x00. Reserved register.
21. Write Register CR10: 0x21. The reference frequency doubler
22. Write Register CR9: 0x70. With the recommended loop
23. Write Register CR8: 0x00. Reserved register.
24. Write Register CR7: 0x0X. Set according to Equation 1 in
Write Register CR30: 0x00. Set attenuator to 0 dB gain.
Write Register CR29: 0x00. Modulator is powered down.
The modulator is powered down by default to ensure that
no spurious signals can occur on the RF output when the
PLL is carrying out its first acquisition. The modulator
should be powered up only when the PLL is locked.
Write Register CR28: 0x01. Power up the internal VCO.
Write 0x21 if using an external VCO.
Write Register CR27: 0x00. Power down the LO monitor
and select the internal VCO. Write 0x08 to select an
external VCO.
Write Register CR26: 0x00. Reserved register.
Write Register CR25: 0x32. Reserved register.
Write Register CR24: 0x18. Enable autocalibration.
Write Register CR23: 0x70. Enable lock detector and
choose the recommended lock detect timing.
Write Register CR22: 0x00. Reserved register.
enabled, even when TXDIS is asserted.
is enabled, and the 5-bit divider and R/2 divider are bypassed.
filter component values and R
Figure 71, the charge pump current is set to 2.5 mA for
a loop bandwidth of 50 kHz.
the Theory of Operation section. Also sets the MUXOUT
pin to tristate.
SET
= 4.7 kΩ, as shown in
Rev. 0 | Page 31 of 40
25. Write Register CR6: 0xXX. Set according to Equation 1 in
26. Write Register CR5: 0x00. Disable the 5-bit reference divider.
27. Write Register CR4: 0x01. Reserved register.
28. Write Register CR3: 0x0X. Set according to Equation 1 in
29. Write Register CR2: 0xXX. Set according to Equation 1 in
30. Write Register CR1: 0xXX. Set according to Equation 1 in
31. Write Register CR0: 0xXX. Set according to Equation 1 in
32. Monitor the LDET output or wait 170 μs to ensure that the
33. Write Register CR29: 0x01. Power up modulator. The write
Example—Changing the LO Frequency
Following is an example of how to change the LO frequency
after the initialization sequence. Using an example in which
the PLL is locked to 1200 MHz, the following conditions apply:
•
•
The INT registers contain the following values:
Register CR7 = 0x00 and Register CR6 = 0x3C
The FRAC registers contain the following values:
Register CR3 = 0x00, Register CR2 = 0x00,
Register CR1 = 0x00, and Register CR0 = 0x00
To change the LO frequency to 1230 MHz, the divide ratio N
must be set to 61.5. Therefore, INT must be set to 61 decimal
and FRAC must be set to 16777216 by writing to the following
registers:
1.
2.
Note that Register CR0 should be the last write in this sequence.
Writing to Register CR0 causes all double-buffered registers to
be updated, including the INT and FRAC registers, and starts a
new PLL acquisition.
If the cumulative frequency step is 100 kHz or less, the user can
turn off autocalibration. This process involves an additional
write of 0x19 to Register CR24, resulting in a smoother
frequency step and shorter acquisition time.
the Theory of Operation section.
the Theory of Operation section.
the Theory of Operation section.
the Theory of Operation section.
the Theory of Operation section. Register CR0 must be the
last register written for all the double-buffered bit writes to
take effect.
PLL is locked.
to Register CR29 does not need to be followed by a write to
Register CR0 because this register is not double-buffered.
f
Divide ratio N = 60, so INT = 60 decimal and FRAC = 0
Set the INT registers as follows:
Register CR7 = 0x00, Register CR6 = 0x3D
Set the FRAC registers as follows:
Register CR3 = 0x01, Register CR2 = 0x00,
Register CR1 = 0x00, Register CR0 = 0x00
PFD
= 20 MHz (assumed)
ADRF6750