ADRF6750 Analog Devices, Inc., ADRF6750 Datasheet - Page 8

• Manufacturer Part Number: ADRF6750
• Description: 950 Mhz To 1575 Mhz Quadrature Modulator With Integrated Fractional-n Pll And Vco
• Manufacturer: Analog Devices, Inc.

ADRF6750
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
11, 55, 56, 41, 42, 1
12
13, 14, 15, 16, 31,
36
6, 19, 20, 21, 24, 37,
39, 40, 46, 47, 49,
50, 51, 52, 53, 54
32
2, 3
4, 5
33, 34, 35
38
7
9
Mnemonic
VCC1 to VCC4
REGOUT
VREG1 to
VREG6
AGND
DGND
IBBP, IBBN
QBBN, QBBP
CCOMP1 to
CCOMP3
VTUNE
RSET
CP
Description
Positive Power Supplies for I/Q Modulator. Apply a 5 V power supply to VCC1, which should be
decoupled with power supply decoupling capacitors. Connect VCC2, VCC3, and VCC4 to the same
5 V power supply.
3.3 V Output Supply. Drives VREG1, VREG2, VREG3, VREG4, VREG5, and VREG6.
Positive Power Supplies for PLL Synthesizer, VCO, and Serial Port. Connect these pins to REGOUT
(3.3 V) and decouple them separately.
Analog Ground. Connect to a low impedance ground plane.
Digital Ground. Connect to the same low impedance ground plane as the AGND pins.
Differential In-Phase Baseband Inputs. These high impedance inputs must be dc-biased to approx-
imately 500 mV dc and should be driven from a low impedance source. Nominal characterized ac
signal swing is 450 mV p-p on each pin. This results in a differential drive of 0.9 V p-p with a 500 mV
dc bias, resulting in a single sideband output power of approximately −1.6 dBm. These inputs are
not self-biased and must be externally biased.
Differential Quadrature Baseband Inputs. These high impedance inputs must be dc-biased to
approximately 500 mV dc and should be driven from a low impedance source. Nominal charac-
terized ac signal swing is 450 mV p-p on each pin. This results in a differential drive of 0.9 V p-p with
a 500 mV dc bias, resulting in a single sideband output power of approximately −1.6 dBm. These
inputs are not self-biased and must be externally biased.
Internal Compensation Nodes. These pins must be decoupled to ground with a 100 nF capacitor.
Control Input to the VCO. This voltage determines the output frequency and is derived from
filtering the CP output voltage.
Charge Pump Current Set. Connecting a resistor between this pin and ground sets the maximum
charge pump output current. The relationship between I
where R
Charge Pump Output. When enabled, this output provides ±I
turn, drives the internal VCO.
I
CPmax
REGOUT
NOTES
1. CONNECT EXPOSED PAD TO GROUND PLANE VIA
VREG1
VREG2
A LOW IMPEDANCE PATH.
QBBN
QBBP
AGND
VCC4
RSET
VCC1
IBBP
IBBN
SET
=
LF3
LF2
CP
23
R
= 4.7 kΩ and I
SET
10
11
12
13
14
5 .
1
2
4
5
6
7
8
9
3
Figure 4. Pin Configuration
PIN 1
INDICATOR
Rev. 0 | Page 8 of 40
ADRF6750
(Not to Scale)
TOP VIEW
CP max
= 5 mA.
42 VCC3
41 VCC3
40 AGND
39 AGND
38 VTUNE
37 AGND
36 VREG6
35 CCOMP3
34 CCOMP2
33 CCOMP1
32 DGND
31 VREG5
30 CLK/SCL
29 SDI/SDA
CP
and R
CP
to the external loop filter, which, in
SET
is as follows: