MB15E07SL Fujitsu Media Devices, MB15E07SL Datasheet - Page 8

• Manufacturer Part Number: MB15E07SL
• Description: Single Serial Input PLL Frequency Synthesizer On-Chip 2.5 GHz Prescaler
• Manufacturer: Fujitsu Media Devices

8
MB15E07SL
1. Pulse Swallow Function
The divide ratio can be calculated using the following equation:
f
2. Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference divider
and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE signal pin is taken high,
stored data is latched according to the control bit data as follows:
Table 1. Control Bit
(1) Shift Register Configuration
VCO
LSB
FUNCTIONAL DESCRIPTION
= [(M
C
N
1
T
CNT
R1 to R14
SW
FC
LDS
CS
Note: Start data input with MSB first.
f
N
A
f
R
M
VCO
OSC
Programmable Reference Counter
Control bit (CNT)
R
2
1
N) + A]
: Output frequency of external voltage controlled oscillator (VCO)
: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
: Preset divide ratio of binary 7-bit swallow counter (0
: Output frequency of the reference frequency oscillator
: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
: Preset divide ratio of modulus prescaler (32 or 64)
R
3
2
H
L
: Control bit
: Divide ratio setting bit for the programmable reference counter (3 to 16,383) [Table 2]
: Divide ratio setting bit for the prescaler (32/33 or 64/65)
: Phase control bit for the phase comparator
: LD/f
: Charge pump current select bit
f
R
4
3
OSC
OUT
R
signal select bit
5
4
R (A < N)
R
6
5
For the programmable reference divider
For the programmable divider
R
7
6
R
8
7
Data Flow
R
9
8
10
R
9
Destination of serial data
11
10
R
12
11
R
A
13
12
R
127)
14
13
R
15
14
R
SW FC
16
17
[Table 1]
[Table 5]
[Table 8]
[Table 7]
[Table 6]
LDS
18
MSB
CS
19