RC2324DPL ETC, RC2324DPL Datasheet - Page 18

• Manufacturer Part Number: RC2324DPL
• Description: Single Device Data/fax Modem Data Pump
• Manufacturer: ETC

2-8
2.0 Hardware Interface
Table 2-2. Hardware Interface Signal Definitions (Continued)
MODEO (DSP)
TDACO (DSP),
TSTBO (DSP),
TRSTO (DSP),
MODEI (IA)
TDACI (IA)
TRSTI (IA)
TSTBI (IA)
EYESYNC
(RRSTO)
EYECLK
SLEEP1
SLEEP
AGCIN
Label
EYEX,
RFILO
SPKR
EYEY
I/O Type
O(DF)
OA
OB
OA
OB
MI
MI
MI
MI
MI
MI
IA
SPEAKER INTERFACE
Speaker Analog Output. The SPKR output reflects the received analog input signal. The
SPKR on/off and three levels of attenuation are controlled by interface memory bits.
When the speaker is turned off, the SPKR output is clamped to the voltage at the VC
pin. The SPKR output can drive an impedance as low as 300 ohms. In a typical
application, the SPKR output is an input to an external LM386 audio power amplifier.
SLEEP MODE SIGNALS
Sleep Mode Output and Sleep Mode Input. SLEEP output high indicates the DSP is
operating in its normal mode. SLEEP low indicates that the DSP is in the sleep mode.
This signal must be connected to the SLEEP1 input to power down the IA in the sleep
mode. SLEEP can also be used to control power to other devices (e.g., as a speaker
enable).
DIAGNOSTIC SIGNALS
Four signals provide the timing and data necessary to create an oscilloscope quadrature
eye pattern. The eye pattern is simply a display of the received baseband constellation.
By observing this constellation, common line disturbances can usually be identified.
Eye Pattern Data X and Eye Pattern Data Y. The EYEX and EYEY outputs provide two
serial bit streams containing data for display on the oscilloscope horizontal (X) axis and
vertical (Y) axis, respectively. This serial digital data can be converted to analog form
using two shift registers and two digital-to-analog converters (DACs).
Eye Pattern Clock. EYECLK is a clock for use by the serial-to-parallel converters. The
EYECLK output is a 7200/9600 Hz clock.
Eye Pattern Sync. EYESYNC is a strobe for word synchronization. The falling edge of
EYESYNC may be used to transfer the 8-bit word from the shift register to a holding
register. Digital-to-analog conversion can then be performed for driving the X and Y
inputs of an oscilloscope.
MODEM INTERCONNECT
Receive Filter Output. RFILO is the output of the internal receive analog filter which
must be connected to AGCIN through a 0.1 µF, 20%, DC decoupling capacitor.
Receive AGC Gain Amplifier Input. See RFILO.
Mode Control. Serial IA mode control bits. Direct modem interconnect line.
Transmitter DAC Signal. Transmitter serial digital DAC signal. Direct modem
interconnect line.
Transmitter Strobe. Transmitter 576 kHz digital timing reference. Direct modem
interconnect line.
Transmitter Reset. Transmitter 7200/9600 Hz digital timing reference. Direct modem
interconnect line.
D96V24DSA
Signal/Definition
Single Device Data/Modem Data Pump
RC96V24DP