GS1515-CQM Gennum Corporation, GS1515-CQM Datasheet - Page 11

• Manufacturer Part Number: GS1515-CQM
• Description: Hd-linx(tm) HDTV Serial Digital Reclocker
• Manufacturer: Gennum Corporation

PHASE LOCK
The phase lock circuit is used to determine the phase
locked condition. It is done by generating a quadrature
clock by delaying the in-phase clock (the clock whose
falling edge is aligned to the data transition) by 166ps
(0.25UI at 1.5GHz) with the tolerance of 0.05UI. When the
PLL is locked, the falling edge of the in-phase clock is
aligned with the data edges as shown in Figure 18. The
quadrature clock is in a logic high state in the vicinity of
input data transitions. The quadrature clock is sampled and
latched by positive edges of the data transitions. The
generated signal is low pass filtered with an RC network.
The R is an on-chip 20kΩ resistor and C
capacitor (recommended value 10nF). The time constant is
about 67µs, or more than a video line.
If the signal is not locked, the data transition phase could
be anywhere with respect to the internal clock or the
quadrature clock. In this case, the normalized filtered
sample of the quadrature clock will be 0.5. When VCO is
locked to the incoming data, data will only sample the
quadrature clock when it is logic high. The normalized
filtered sample quadrature clock will be 1.0. We chose a
threshold of 0.66 to generate the phase lock signal.
Because the threshold is lower than 1, it allows jitter to be
bigger than 0.5UI before the phase lock circuit reads it as
“not phase locked”.
INPUT JITTER INDICATOR (IJI)
This signal indicates the amount of excessive jitter (beyond
the quadrature clock window 0.5UI), which occurs beyond
the quadrature clock window (see Figure 18). All the input
data transitions occurring outside the quadrature clock
window, will be captured and filtered by the low pass filter
as mentioned in the Phase Lock section. The running time
IN-PHASE CLOCK
INPUT DATA
WITH JITTER
QUADERATURE
CLOCK
PLCAP SIGNAL
PLCAP SIGNAL
PHASE ALIGNMENT
0.25UI
EDGE
Fig. 18 PLL Circuit Principles
RE-TIMING
EDGE
0.8UI
PL
is an external
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average of the ratio of the transitions inside the quadrature
clock and outside the quadrature is available at the PLCAP/
PLCAP pins. A signal, IJI, which is the buffered signal
available at the PLCAP is provided so that loading does not
effect the filter circuit. The signal at IJI is referenced with the
power supply such that the factor V
process and power supply for a given input jitter
modulation. The IJI signal has 10kΩ output impedance.
Figure 19 shows the relationship of the IJI signal with
respect to the sine wave modulated input jitter.
LOCK LOGIC
Logic is used to produce the PLL_LOCK signal which is
based on the LFS signal and phase lock signal. When there
is not any data input, the integrator will charge and
eventually saturate at either end. By sensing the saturation
of the integrator, it is determined that no data is present. If
either data is not present or phase lock is low, the lock
signal is made low. Logic signals are used to acquire the
frequency by sweeping the integrator. Injecting a current
P-P SINE WAVE JITTER IN UI
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
Fig. 19 Input Jitter Indicator (Typical at T
0.00
0.00
0.15
0.30
0.39
0.45
0.48
0.52
0.55
0.58
0.60
0.63
0.20
INPUT JITTER (UI)
0.40
IJI
/V
CC
IJI VOLTAGE
is a constant over
0.60
4.75
4.75
4.75
4.70
4.60
4.50
4.40
4.30
4.20
4.10
3.95
A
= 25°C)
522 - 23 - 03
0.80