GS1515-CQM Gennum Corporation, GS1515-CQM Datasheet - Page 16

• Manufacturer Part Number: GS1515-CQM
• Description: Hd-linx(tm) HDTV Serial Digital Reclocker
• Manufacturer: Gennum Corporation

OTHER LAYOUT CONSIDERATIONS
The GS1515 is a robust re-timing solution. The layout
should be done such that VCO (GO1515) is close to the
chip minimizing LFA and VCO traces between GS1515 and
GO1515. It is recommended to use the other side of the
PCB board whenever possible. The short trace of LFA will
reduce noise coupling to the control pin of the VCO. The
VCO trace should also be short to reduce EMI radiation
from a 1.5GHz clock source. Digital switching noise from
CMOS chips should be avoided for best performance. This
could be done by providing a moat of at least 50mil wide in
all the planes (the GND, V
be able to see through the moat when the PCB is
fabricated). The power supply to the GS1515 Island should
be provided through ferrite beads to reject the power
supply spikes.
TABLE 3: Application Debugging
522 - 23 - 03
Output Jitter > 80ps
Errors being generated
PROBLEM
CC
Wrong way of measuring jitter.
Bad source / trigger reference signal.
Power supply noise generated either by on board
digital circuit or switch mode DC power supply.
Bypass mode activated.
Bad input jitter.
and signal layers) (One should
POSSIBLE REASON
16 of 17
In applications where an adaptive equalizer is used with the
GS1515, extra care should be taken to avoid any noise
coupling between these two devices. The following
recommendations should be followed as layout guides
lines. Please refer to the layouts of the EB1515/04 and note
the following:
1. The use of power supply islands for GS1504 Adaptive
2. The position of ferrite beads for power supply noise
3. The ground under the transmission line for GS1504 and
4. The transmission line decoupling at the GS1515 end to
5. The isolation moat around the transmission line
Equalizer.
filtering.
GS1515 interface.
the transmission line ground.
reference ground.
Follow jitter measuring procedure as shown in Fig
12.
Follow jitter measuring procedure as shown in Fig
12.
Shut down the digital circuit and power the board
from clean voltage regulated supply. The
acceptable noise in the V
problem is resolved, filter high frequency noise with
ferrite beads and low frequency noise with Inductor
and Capacitor. The source of jitter could also be
found using diagnostic signal DM as mentioned in
the section JITTER DEMODULATION.
Apply logic high at the BYPASS pin.
A.
B.
Configure into bypass mode and look for
output jitter under infinite persistence for
about 5 minutes in a sampling scope, if total
jitter including random shots is more than
0.5UI, input jitter is out of specification. Debug
circuit, which is driving GS1515.
Probe IJI by a low frequency digital scope to
capture any glitch. If glitches are not
identified, remove the 10nF PLCAP between
PLCAP and PLCAP. If glitches are identified,
then the sum of jitter of the reclocker and the
source is more than 0.5UI. Achieve reclocker
jitter around 0.1UI or less and reduce the
source jitter less than 0.4UI.
SOLUTION
CC
is 5mVp-p. If the