GS1515-CQM Gennum Corporation, GS1515-CQM Datasheet - Page 15

• Manufacturer Part Number: GS1515-CQM
• Description: Hd-linx(tm) HDTV Serial Digital Reclocker
• Manufacturer: Gennum Corporation

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Fig. 27 Power Layer
Fig. 28 Bottom Copper Layer
EXTERNAL PCB AFFECTS
EXTERNAL PCB AFFECTS
EXTERNAL PCB AFFECTS
EXTERNAL PCB AFFECTS
RETURN LOSS
In the application where the GS1515 directly drives a cable,
it is possible to achieve an output return loss (ORL) of about
17dB to 1.485GHz. Care should be taken with the PCB
layout. It is suggested to use the EB1515 as a reference
layout. The use of very small ‘608’ surface mount
components and short distances between the components
will help in designing high frequency circuits. Openings in
the ground plane helps reduce PCB parasitic capacitance.
For best matching, a 10nH inductor in parallel with a 75Ω
resistor and a 1.5pF capacitor matches the 75Ω cable
impedance. The inductor and resistor cancel the parasitic
capacitance while the capacitor cancels the inductive effect
of the bond wire. In order to verify the performance of any
layout, a return loss measurement should be done by
shorting the inductor with a piece of wire,
without the
GS1515 installed.
Unless the artwork is an exact copy of the recommended
Fig. 29 Compensated Output Return Loss at Logic HIGH
layout, every design should be verified for output return
loss. Changes in the layout should be tweaked until a return
loss of 25dB is attained while the GS1515 is not mounted
and L
is shorted. Once the device is mounted, different
COMP
inductors
should
be
used
to
match
the
parasitic
capacitance of the IC. When the right inductor is used,
maximum return loss between 5MHz to 800MHz is
achievable. Then the shunt capacitor between of 0.5pF to
1.5pF should be tried to increase the return loss between
800MHz and 1.5GHz. The larger inductor causes slower
rise/fall time. The larger shunt capacitor causes a kink in the
output waveform. Thus, the waveform must be verified to
meet SMPTE 292M specifications.
Since there are two levels at the output, depending upon
the output state (logic high or low), measurement should be
done by latching the outputs in both states. Since the actual
output node voltages are different when a stream of data
passing as compared to the static situation created to
measure return loss, an interpolation is necessary. See the
GS1508 Preliminary Data Sheet for more information.
Fig. 30 Compensated Output Return Loss at Logic LOW
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