GS1522 Gennum Corporation, GS1522 Datasheet - Page 10

• Manufacturer Part Number: GS1522
• Description: Hd-linx (tm) THDTV Serial Digital Serializer
• Manufacturer: Gennum Corporation

pump drops with reducing data transitions. During
pathological signals, the data transition density reduces
from 0.5 to 0.05 but the slew PLL’s performance does not
change significantly.
Because most of the PLL circuitry is digital, it is very robust
as digital systems are generally more robust than their
analog counterparts. Signals which represent the internal
functionality, like DM (86), can be generated without adding
additional artifacts. Thus, system debugging is possible
with these features.
The complete slew PLL is made up of several blocks
including the phase detector, the charge pump and an
external Voltage Controlled Oscillator (VCO) which are
described in the following sections. Phase lock loop
frequency synthesis and lock logic are also described.
5.1. Phase Detector
The phase detector portion of the slew PLL used in the
GS1522 is a bi-level digital phase detector. It indicates
whether the data transition occurred before or after with
respect to the falling edge of the internal clock. When the
phase detector is locked, the data transition edges are
aligned to the falling edge of the clock. The input data is
then sampled by the rising edge of the clock, as shown in
Figure 15. In this manner, the allowed input jitter is 1UI p-p
in an ideal situation. However, due to setup and hold time,
the GS1522 typically achieves 0.8UI p-p input jitter
tolerance without causing any errors in this block. When the
signal is locked to the internal clock, the control output from
the phase detector is refreshed at the transition of each
rising edge of the data input. During this time, the phase of
the clock drifts in one direction.
GENNUM CORPORATION
0.2
0.1
0.0
0.2
0.1
0.0
LINEAR (CONVENTIONAL) PLL RESPONSE
Fig. 14 PLL Characteristics
SLEW PLL RESPONSE
INPUT
INPUT
OUTPUT
OUTPUT
10
During pathological signals, the amount of jitter that the
phase detector will add can be calculated. By choosing the
proper loop bandwidth, the amount of phase detector
induced jitter can also be limited. Typically, for a 1.41MHz
loop bandwidth at 0.2UI input jitter modulation, the phase
detector induced jitter is about 0.015UIp-p. This is not
significant, even in the presence of pathological signals.
5.2. Charge Pump
The charge pump in a slew PLL is different from the charge
pump in a linear PLL. There are two main functions of the
charge pump: to hold the frequency information of the input
data and to provide a binary control voltage to the VCO.
The charge pump holds the frequency information of the
input data. This information is held by C
connected between LFS (82) and LFS (84). C
connected between LFS and LFA_V
remove common mode noise. Both C
have the same value.
The charge pump provides a binary control voltage to the
VCO depending upon the phase detector output. The
output pin LFA (90) controls the VCO. Internally there is a
500Ω pull-up resistor which is driven with a 100µA current
called Ι
drive proportional to the voltage across the C
at the same node. The voltage at the LFA node is
V
Because of the integrator, Ι
Ι
often as a clock period. In the locked position, the average
voltage at LFA (V
generates frequency ƒ equal to the data rate clock
frequency. Since Ι
100µA, there are two levels generated at the LFA output.
5.3. VCO
The GO1515 is an external hybrid VCO which has a centre
frequency of 1.485GHz. It is guaranteed to provide
1.485/1.001GHz within the control voltage (3.1V – 4.65V) of
the GS1522 over process, power supply and temperature.
P
LFA_VCC
INPUT CLOCK
WITH JITTER
IN-PHASE CLOCK
can change at the positive edge of the data transition as
PHASE ALIGNMENT
P
OUTPUT DATA
. Another analog current Ι
- 500(Ι
Fig. 15 Phase Detector Characteristics
P
EDGE
+Ι
P
F
LFA_VCC
) at any time.
is changing all the time between 0A and
RE-TIMING
EDGE
– 500(Ι
F
changes very slowly whereas
0.8UI
P
/2+Ι
F
, with 5mA maximum
CP1
F
EE
) is such that VCO
(89), is used to
and C
CP1
CP1
CP2
, is applied
CP2
522 - 26 - 02
, which is
which is
should