GS1522 Gennum Corporation, GS1522 Datasheet - Page 12

• Manufacturer Part Number: GS1522
• Description: Hd-linx (tm) THDTV Serial Digital Serializer
• Manufacturer: Gennum Corporation

The synchronous lock time increases with reduced
bandwidth. Nominal synchronous lock time is equal to
[
bandwidth
25.72kHzUI,
0.3535/25.72k = 13.75µs. Since the C
also charged, it is measured to be about 11µs which is
slightly less than the calculated value of 13.75µs.
The Kƒ of the VCO (GO1515) is specified with a minimum of
11MHz/V and maximum of 21MHz/V which is about ±32%
variation. The 500 x Ι
bandwidth factor varies by approximately ±45% when no
R
variability for lower bandwidths increases by an additional
±30%.
The C
reduced bandwidths. Smaller C
result in jitter peaking, lower stability, less probability of
locking but at the same time lowering the asynchronous
lock time. Therefore, there is a trade-off between
asynchronous lock time and jitter peaking/stability. These
capacitors should be as large as possible for the allowable
lock time and should be no smaller than the allowed value.
With the recommended values, jitter peaking of less than
0.1dB has been measured at the lower loop bandwidth as
shown in Figure 17. At higher loop bandwidths, it is difficult
to measure jitter peaking because of the limitation of the
measurement unit.
However,
capacitors can be used, over-damping of the loop response
occurs. An accurate jitter peaking measurement of 0.1dB
for the GS1522 requires the modulation source to have a
constant amount of jitter modulation index (within 0.1dB or
1.2%) over the frequency range beyond the loop
bandwidth.
GENNUM CORPORATION
0.25
CP1
and C
×
CP1
2
and C
/Bandwidth
CP3
because
factor
are used. Ι
the
Fig. 17 Typical Jitter Peaking
CP2
(282.9kHzUI)
capacitors should be changed with
P
relatively
/2 varies about ±10%. The resulting
synchronous
factor].
P
by itself may vary by 30% so the
CP1
larger
That
CP1
yields
and C
, C
lock
is,
C
CP2
CP1
CP2
1.25µs.
and C
the
and
capacitors
time
default
CP3
C
For
are
CP2
is
12
It has been determined that for 282.9kHzUI, the minimum
value of the C
than 0.5µF. For added margin, 1µF capacitors are
recommended. The 1µF value gives a lock time of about
60ms in one attempt. For 25.72kHzUI, these capacitors
should be no less than 5.6µF. This results in 340ms of lock
time. If necessary, extra margin can be built by increasing
these capacitors at the expense of a longer asynchronous
lock time.
Bandwidths lower than 129kHz at 0.2UI modulation have
not been characterized, but it is believed that the
bandwidth could be further lowered (contact Gennum’s
Video Products Applications for further details). Since a
lower bandwidth has less correction for noise, extra care
should be taken to minimize board noise. Figures 18 and 19
show the two measured loop bandwidths at these two
settings. Table 2 summarizes the two bandwidth settings.
Fig. 18 Typical Jitter Transfer Curve at Setting A in Table 2
Fig. 19 Typical Jitter Transfer Curve at Setting B in Table 2
CP1
and C
CP2
capacitors should be no less
522 - 26 - 02