GS1522 Gennum Corporation, GS1522 Datasheet - Page 13

• Manufacturer Part Number: GS1522
• Description: Hd-linx (tm) THDTV Serial Digital Serializer
• Manufacturer: Gennum Corporation

TABLE 2: Loop Bandwidth Setting Options
8. PHASE LOCK
The phase lock circuit is used to determine the phase
locked condition. It is done by generating a quadrature
clock by delaying the in-phase clock by 166ps (0.25UI at
1.5GHz) with the tolerance of 0.05UI. The in-phase clock is
the clock whose falling edge is aligned to the data
transition. When the PLL is locked, the falling edge of the in-
phase clock is aligned with the data edges as shown in
Figure 20. The quadrature clock is in a logic HIGH state in
the vicinity of input data transitions. The quadrature clock is
sampled and latched by positive edges of the data
transitions. The generated signal is low pass filtered with an
RC network. The R is an on-chip 6.67kΩ resistor and C
an internal capacitor (31pF). The time constant is about
200ns.
If the signal is not locked, the data transition phase could
be anywhere with respect to the internal clock or the
quadrature clock. In this case, the normalized filtered
sample of the quadrature clock is 0.5. When VCO is locked
to the incoming data, data will only sample the quadrature
clock when it is logic HIGH. The normalized filtered sample
quadrature clock is 1.0. We chose a threshold of 0.66 to
generate the phase lock signal. Because the threshold is
lower than 1, it allows jitter to be greater than 0.5UI before
the phase lock circuit reads it as “not phase locked”.
GENNUM CORPORATION
A
B
INPUT CLOCK
WITH JITTER
QUADERATURE
CLOCK
PLCAP SIGNAL
PLCAP SIGNAL
IN-PHASE CLOCK
PHASE ALIGNMENT
RCP1
Open
50
0.25UI
EDGE
Fig. 20 PLL Circuit Principles
CCP3
Open
1.0
RE-TIMING
EDGE
CCP1
1.0
5.6
0.8UI
CCP2
1.0
5.6
282.9kHz
25.72kHz
FACTOR
BW
PL
is
13
BW at 0.2 UI JITTER
9. INPUT JITTER INDICATOR (IJI)
This signal indicates the amount of excessive jitter which
occurs beyond the quadrature clock window (greater than
0.5UI, see Figure 19). All the input data transitions
occurring outside the quadrature clock window are
captured and filtered by the low pass filter as mentioned in
section 8, Phase Lock. The running time average of the
ratio of the transitions inside the quadrature clock and
outside the quadrature is available at the PLCAP/PLCAP
pins (87 and 85). IJI, which is the buffered signal available
at the PLCAP, is provided so that loading does not effect
the filter circuit. The signal at IJI is referenced with the
power supply such that the factor V
process and power supply for a given input jitter
modulation. The IJI signal has 10kΩ output impedance.
Figure 21 shows the relationship of the IJI signal with
respect to the sine wave modulated input jitter.
TABLE 3: IJI Voltage as a Function of Sinusoidal Jitter
P-P SINE WAVE JITTER IN UI
MODULATION
1.41MHz
129kHz
INDEX
0.00
0.15
0.30
0.39
0.45
0.48
0.52
0.55
0.58
0.60
0.63
ASYNCHRONOUS
340ms
60ms
IJI
/V
CC
IJI VOLTAGE
is a constant over
SYNCHRONOUS
4.75
4.75
4.75
4.70
4.60
4.50
4.40
4.30
4.20
4.10
3.95
1.25µs
11.0µs
522 - 26 - 02