S8501 AMCC (Applied Micro Circuits Corp), S8501 Datasheet - Page 15

• Manufacturer Part Number: S8501
• Description: Hd-sdi Data Retimer
• Manufacturer: AMCC (Applied Micro Circuits Corp)

Timing
This section will detail the timing requirements of all
of the signals on the interface. All timing is measured
into a lumped 15pF capacitive load.
RCLK Timing
When LOCKREFN is pulled low, RCLK should be in
local phase lock with REFCLK within 500 s.
LOCKREFN, when activated, shall stay low for a du-
ration of at least 500 s if receiver frequency lock is to
be expected. After local phase lock has been ac-
quired, and when LPEN is high, 2500 baud times
after LOCKREFN is driven high, RCLK shall be in
phase lock with REFCLK. After local phase lock has
been acquired, and when LPEN is low, 250 baud
times after LOCKREFN is driven high, RCLK shall be
in phase lock with the incoming serial data stream.
December 10, 1999 / Revision C
HIGH DEFINITION SERIAL DIGITAL INTERFACE (HD-SDI) CHIPSET
Table 12. Serial Data Input Timing Table (RLX, RLY; RX, RY)
P
n I
T
R
a
o
a r
S
p
D
T
e l
t u
R
m
L
a r
,
O
J
C
e
R
n
t t i
K
e t
Figure 9. Transmitter Timing Diagram
S
c
D
r e
e
D[0:19] 20 BIT DATA
s r
F
S
D
n I
a
B
o l l
r e
E
a
p
a t
R
t u
l a i
c
DATA OUT
t a
<
a
d
1
d
o i
REFCLK
q
a
E
SERIAL
a
i u
a t
n
1 -
a t
D
t i s
t a
e
2
e
n i
s
o i
y
e r
c
p
e
n
i r
u
c
o
o l
r t
t p
e
p
v i
k c
e
s i
o i
D0
r e
n
e
n
n i
i t
a
m
n i
1
g
n
p
e
d
2
u
f t
f
l l a
3
r o
4
5
M
4
6
—
—
7
n i
1
7
8
T 1
D9
M
3
2
0
—
D10
a
5 .
When a 74.25 MHz module is in frequency lock (ei-
ther with REFCLK or a serial data stream) RCLK
shall never have a high level duration (>2.0v) which
is less than 4.3 ns, nor a low level duration (<0.8v)
which is less than 4.3 ns (no clock shivering shall
occur). When the S8501 is in frequency lock (either
with REFCLK or a serial data stream) and LOCKREFN
has been inactive for at least 2500 baud times the
minimum instantaneous period shall always be greater
that 13.0 ns. When the PLL is adjusting to a new
phase or a new frequency, where both the old and
new frequencies are valid SMPTE 292M frequencies,
RCLK shall never have a period less than 13.0 ns.
0
x
T 2
11
12
U
i n
p
µ
p
13
s
s
s
s t
14
15
C
2
0
16
o
%
n
17
d
o t
t i
18
o i
8
D19
0
n
%
s
.
S8401/S8501
15