S8501 AMCC (Applied Micro Circuits Corp), S8501 Datasheet - Page 3

• Manufacturer Part Number: S8501
• Description: Hd-sdi Data Retimer
• Manufacturer: AMCC (Applied Micro Circuits Corp)

Parallel/Serial Conversion
The parallel-to-serial converter takes in 20-bit wide
data from the input latch and converts it to a serial
data stream. Parallel data is latched into the transmit-
ter on the positive going edge of REFCLK. The data
is then clocked synchronous to the clock synthesis
unit serial clock into the serial output shift register.
The shift register is clocked by the internally gener-
ated bit clock which is 20 times the REFCLK input
frequency. The state of the serial outputs is controlled
by the output enable pins, OE0 and OE1. D[0] is
transmitted first.
Figure 4. S8501 Functional Block Diagram
December 10, 1999 / Revision C
HIGH DEFINITION SERIAL DIGITAL INTERFACE (HD-SDI) CHIPSET
LOCKREFN
REFCLK
LPEN
RLX
RLY
RX
RY
2:1
RECOVERY
PLL CLOCK
Reference Clock Input
The reference clock input (REFCLK) must be supplied
with a PECL single-ended AC coupled crystal clock
source with 100 PPM tolerance to assure that the trans-
mitted data meets the SMPTE 292M Specification
frequency limits. The internal serial clock is frequency
locked to the reference clock. Refer to Table 1 for
reference clock frequency.
Table 1. Transmitter Operating Mode
D
BITCLK
(
(
(
(
(
a
M
M
M
M
M
1
a t
4
b
b
b
b
b
8
R
p
p
p
p
p
5
D
) s
) s
) s
) s
) s
a
REGISTER
e t
SHIFT
DIVIDER
W
W
W
W
W
(
(
(
W
(
(
B
B
B
B
B
2
d i
d i
d i
d i
d i
o
t i
t i
t i
t i
t i
0
d r
) s
) s
) s
) s
) s
h t
h t
h t
h t
h t
D
F
F
F
F
F
R
e r
e r
e r
e r
e r
Q
e
C
C
C
C
C
(
(
(
(
(
7
e f
M
M
M
M
M
q
q
q
q
q
4
o l
o l
o l
o l
o l
u
u
u
u
u
e r
H
H
H
H
H
2 .
20
c
c
c
c
c
e
e
e
e
e
) z
) z
) z
) z
) z
n
5
k
k
k
k
k
n
n
n
n
n
c
c
c
c
c
c
e
y
y
y
y
y
S8401/S8501
LOCKDETN
D[19:0]
RCLK
RCLKN
T
C
F
F
F
F
F
e r
e r
e r
e r
e r
L
(
(
(
(
(
K
7
M
M
M
M
M
q
q
q
q
q
4
T /
u
u
u
u
u
H
H
H
H
H
2 .
e
e
e
e
e
C
) z
) z
) z
) z
) z
5
n
n
n
n
n
L
c
c
c
c
c
K
y
y
y
y
y
N
3