CS98000 Cirrus Logic, Inc., CS98000 Datasheet - Page 20

• Manufacturer Part Number: CS98000
• Description: DVD Video Processor
• Manufacturer: Cirrus Logic, Inc.

3.2.13
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3.3
The CS98000 includes two powerful, proprietary
32-bit RISC processors, RISC0 and RISC1, with
optimizing C compiler support and source level de-
bugger. The RISC processors fully support many
Real Time Operation Systems (RTOS). The DVD
application user interface resides on RISC1 and is
customer programmable. The real time control of
low level DVD functions is performed by RISC0.
RISC1 gains access to system resources controlled
by RISC0 via calls through an Applications Pro-
gramming Interface, See the CS98000 Software
API. All RISC0 firmware, API and sample applica-
tion code are supplied with the CS98000.
In addition to being compatible with the standard
MIPS
sors also have a MAC engine, which performs mul-
tiply/accumulate in 2 cycles in a pipelined fashion
with C support, effectively achieving single cycle
throughout. The RISC0 processor coordinates on-
chip multi-threaded tasks, as well as system activi-
ties such as remote control and front panel control.
The DVD application end-user interface resides on
RISC1, and any modifications to that interface oc-
cur through the CS98000 API.
3.4
The CS98000 contains a proprietary digital signal
processor (DSP), which is optimized for audio ap-
plications. The DSP performs 32-bit simple integer
operations, and has a 24-bit fixed point logic unit,
with a 54-bit accumulator. There are 32 general-
purpose registers, and eight independent address
generation registers, featuring: linear and circular
buffer operations, and dual operand read from
memory. The multiply-accumulator has single-cy-
20
208-pin PQFP packages
All I/O pins are 3 V with 5 V tolerance
Advanced 0.25 micron CMOS technology
Internal processors run at 81 MHz
Supports Low Power modes and clock shutoff
®
RISC Processor
DSP Processor
R3000
System Functions
®
instruction set, the RISC proces-
cle throughput, with two cycle latency. The DSP is
optimized for bit packing and unpacking opera-
tions. The interface to main memory is designed for
handling flexible block sizes and skip counts.
3.5
The DRAM Interface performs the SDRAM con-
trol and arbitration functions for all the other mod-
ules in the CS98000. The DRAM interface services
and arbitrates a number of clients and stores their
code and/or data within the local memory. This ar-
bitration and scheduling guarantees the allocation
of sufficient bandwidth to the various clients. The
DRAM Interface supports up to 32 Mbytes. For a
typical DVD player application, CS98000 requires
8 Mbytes memory space.
Sharing the same interface, CS98000 also supports
FLASH ROM, OTP, or mask ROM interface. Code
is stored in ROM. After the system is booted, the
code is shadowed inside SDRAM for execution.
The FLASH ROM interface is provided so that the
code can be upgraded in the field once the commu-
nications channel is established (via modem port,
CD-R, or serial port). Utility software will be pro-
vided to debug and upgrade code for the system
manufacturer.
3.6
The DMA controller moves data between the exter-
nal memory and internal memory. The external
memory address can be specified using a register,
or in FIFO mode, using start and end address regis-
ters. Separate start/end address registers are used
for DMA read and write operations. The DMA in-
terface also has a block transfer function, which al-
lows for the transfer of one block of data from one
external memory location to another external mem-
ory location. In effect, this feature combines a
DMA read and write into one operation. In addi-
tion, the DMA write operation allows for byte,
short, word, and other types of masking.
Memory Control
Dataflow Control (DMA)
CS98000