CS98100 Cirrus Logic, Inc., CS98100 Datasheet - Page 19

• Manufacturer Part Number: CS98100
• Description: DVD Video Processor With Progressive Scan
• Manufacturer: Cirrus Logic, Inc.

3. FUNCTIONAL DESCRIPTION
3.1
The CS98100 includes a powerful, proprietary 32-
bit RISC processor with optimizing C compiler
support. The RISC has a MIPS-compatible instruc-
tion set, as well as a MAC engine which performs
multiply/accumulate in 2 cycles in a pipelined fash-
ion with C support, effectively achieving single cy-
cle throughout. The CS98100 fully supports many
Real Time Operating Systems (RTOS). The RISC
processor co-ordinates on-chip multi-threaded
tasks, as well as supervises system activities such
as remote control and VFD front panel control.
3.2
The CS98100 contains a proprietary digital signal
processor (DSP) which is optimized for audio ap-
plications. The DSP performs 32-bit simple integer
operations, and has a 24-bit fixed point logic unit,
with a 54-bit accumulator. There are 32 general-
purpose registers, and eight independent address
generation registers, featuring: post-increment
ALU, linear and circular buffer operations, bit re-
verse ALU operations, and dual operand read from
memory. The multiply-accumulator has single-cy-
cle throughput, with two cycle latency. The DSP is
optimized for bit packing and unpacking opera-
tions. The interface to main memory is designed for
bursting flexible block sizes and skip counts.
3.3
The DRAM Interface performs the SDRAM con-
trol and arbitration functions for all the other mod-
ules in the CS98100. The DRAM interface services
and arbitrates a number of clients and stores their
code and/or data within the local memory. This ar-
bitration and scheduling guarantees the allocation
of sufficient bandwidth to the various clients. The
DRAM Interface supports up to 32 MByte. For a
typical DVD player application, CS98100 requires
8 MByte of SDRAM and 1 MByte of FLASH.
RISC Processor
DSP Processor
Memory Control
Sharing the same interface, the CS98100 also sup-
ports flash ROM, OTP, or masked ROM interface.
Code is stored in ROM. After the system is booted,
the code is shadowed inside DRAM for execution.
FLASH ROM interface is provided so that the code
can be upgraded in field once the communication
channel is established via, for example, CD-R or
serial port. Utility software will be provided to de-
bug and upgrade code for the system manufacturer.
3.4
The DMA controller moves data between the exter-
nal memory and an internal memory. The external
memory address can be specified using a register,
or in FIFO mode, using start and end address regis-
ters. Separate start/end address registers are used
for DMA read and write operations. The DMA in-
terface also has a block transfer function, which al-
lows for the transfer of one block of data from one
external memory location to another external mem-
ory location. In effect, combining a DMA read and
write into one operation. In addition, the DMA
write operation allows for byte, short, word, and
other types of masking. A second dedicated DMA
controller provides for fast memory-to-memory
transfers.
3.5
The system control functions are used to coordinate
the activities of the multiple processors, and to pro-
vide the supporting system operations. Four 32-bit
communication registers are available inter-pro-
cessor communication, and eight semaphore regis-
ters are used for resource locking. Timers are
available for general-purpose functions, as well as
more specialized functions such as watchdog tim-
ers and performance monitoring. The large number
of general purpose I/Os offers flexibility in system
configurations.
Three separate serial interfaces, conforming to in-
dustry-standard protocols, are available for a vari-
Dataflow Control (DMA)
System Control Functions
CS98100
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