ACS8509 Semtech Corporation, ACS8509 Datasheet - Page 12

• Manufacturer Part Number: ACS8509
• Description: Synchronous Equipment Timing Source for Sonet or SDH Network Elements
• Manufacturer: Semtech Corporation

Figure 3 Minimum Input Jitter Tolerance (OC-3/STM-1)
Frame Sync and Multi-Frame Sync Clocks (Part of
T
Frame Sync (8 kHz) and Multi-Frame Sync (2 kHz) clocks
are provided on outputs “FrSync” and “MFrSync”. The
FrSync and MFrSync clocks have a 50:50 mark space
ratio. These are driven from the T
synchronized with their counterparts in a second
ACS8509 device (if used), using the technique described
later.
Output Clock Ports
The device supports a set of main output clocks, T
and T
Sync” and “Multi-Frame Sync”. The two main output
clocks, T
and are individually selectable. The two secondary output
clocks, Frame Sync and Multi-Frame Sync, are derived
from T
selectable from a range of pre-defined spot frequencies
and a variety of output technologies are supported, as
defined in Table 10.
Revision 2.00/January 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
OUT0
OUT4
)
OUT0
OUT0
A0
A1
A2
A3
A4
, and a pair of secondary output clocks, “Frame
Note...For inputs supporting G.783
Table 8 Amplitude and Frequency Values for Jitter Tolerance (OC-3/STM-1)
STM-1
. The frequencies of the output clocks are
level
STM
and T
f0
OUT4
2800
Peak to peak amplitude (unit
A0
, are independent of each other
311 39 1.5 0.15
A1
Interval)
f1
A2
OUT0
A3
f2
clock. They are
[9]
compliant sources.)
A4
12 u 178 u 1.6 m 15.6 m
F0
f3
OUT0
F1
FINAL
Page 12
f4
Low-speed Output Clock (T
The T
will provide a TTL/CMOS signal at either 1.544 MHz or
2.048 MHz, depending on the setting of the SONSDHB
pin.
High-speed Output Clock (Part of T
The T
differential and can support clocks up to 155.52 MHz.
Output O2 is a TTL/CMOS output with a choice of 11
different frequencies up to 51.84 MHz. Output O3 is a
TTL/CMOS output with fixed frequency of 19.44 MHz.
Each output is individually configured to operate at the
frequencies shown in Table 10 (configuration must be
consistent between ACS8509 devices for protection-
switching to be effective - output clocks will be phase-
aligned between devices). Using the
cnfg_differential_outputs register, output O1 can be
made to be LVDS or PECL compatible.
F2
OUT4
OUT0
f5
F3
clock is supplied on output port O4. This port
port has multiple outputs. Output O1 is
Frequency (Hz)
0.125
Jitter and Wander Frequency (log scale)
f6
F4
19.3
f7
F5
F8530_003MINIPJITTOLOC3STM1_02
500
f8
F6
ACS8509 SETS
OUT4
6.5 k 65 k 1.3m
)
F7
f9
OUT0
F8
DATASHEET
www.semtech.com
)
F9