MD1050-DCC M-Systems Inc., MD1050-DCC Datasheet - Page 8

• Manufacturer Part Number: MD1050-DCC
• Description: Diskonchip Ide Pro Data Sheet
• Manufacturer: M-Systems Inc.

2.3
Table 2 contains the pin description of DiskOnChip IDE Pro.
7
HD15-HD0
HA2-HA0
DIOW#
DIOR#
CSEL
CS0#
CS1#
RESET#
IORDY
INTRQ
Signal
Pin Description
33,35,36
Pin No.
3-18
23
25
28
37
38
27
31
1
Host Data bus [15:0]. 16-bit bi-directional data input/output bus.
HD15 is the most significant bit, while HD0 is the least significant
bit. This bus carries data, commands and status information
between the host and DiskOnChip IDE Pro. The lower 8 bits are
used for 8-bit register transfers. Data transfers are 16-bits wide.
Host Address bus HA[2:0]: Select the registers in the DiskOnChip
IDE Pro controller.
Device I/O Write: Active low. Gates the data from the bus into
DiskOnChip IDE Pro. The clocking occurs on the rising edge of the
signal.
Device I/O Read: Active low. Gates the data onto the bus from
DiskOnChip IDE Pro. The clocking occurs on the falling edge of
the signal.
Configuration Select: Determines the device configuration as
either Master or Slave. If CSEL is negated, then the device
address is Master; if CSEL is asserted, then the device address is
Slave.
Host Chip Select 0: Active low. Selects the Command Block
registers.
Host Chip Select 1: Active low. Selects the Command Block
registers.
Host reset: Active low.
I/O Ready: Negated by DiskOnChip IDE Pro to extend the host
transfer cycle (Read or Write) when the device is not ready to
respond to a data transfer request.
Interrupt Request: Interrupt request from DiskOnChip IDE Pro to
the host. The output of this signal is tri-stated if the host disables
the interrupt. When asserted, this signal is negated by the device
within 400 nsec of the negation of DIOR# that reads the Status
register. When asserted, this signal is negated by the device within
400 nsec of the negation of DIOW# that writes the Command
register.
DiskOnChip IDE Pro Data Sheet, Rev. 1.5
Table 2: Pin Description
System Interface
Configuration
Control
Description
91-SR-012-01-8L
Signal
Output
Output
Type
Input
Input
Input
Input
Input
Input
Input
I/O