MD4331-d1G-MECH M-Systems Inc., MD4331-d1G-MECH Datasheet

no-image

MD4331-d1G-MECH

Manufacturer Part Number
MD4331-d1G-MECH
Description
Mobile Diskonchip G3 Data Sheet
Manufacturer
M-Systems Inc.
Datasheet
Highlights
Mobile DiskOnChip G3 is one of the industry’s
most efficient storage solutions, using
Toshiba’s 0.13 µm Multi-Level Cell (MLC)
NAND flash technology and x2 technology
from M-Systems®. MLC NAND flash
technology provides the smallest die size by
storing 2 bits of information in a single memory
cell. x2 technology enables MLC NAND to
achieve highly reliable, high-performance data
and code storage with a specially designed error
detection and correction mechanism, optimized
file management, and proprietary algorithms for
enhanced performance.
Further cost benefits derive from the
cost-effective architecture of Mobile
DiskOnChip G3, which includes a boot block
that can replace expensive NOR flash, and
incorporates both the flash array and an
embedded thin controller in a single die.
Mobile DiskOnChip G3 provides:
1
Flash disk for both code and data storage
Low voltage: 1.8V or 3.3 I/O (auto-detect),
3V Core
Hardware protection and security-enabling
features
High capacity: single die - 512Mb (64MB),
dual die - 1Gb (128MB)
Device cascade capacity: up to 2Gb
(256MB)
512Mbit/1Gbit Flash Disk with MLC NAND and
Mobile DiskOnChip G3
M-Systems’ x2 Technology
Preliminary Data Sheet, Rev. 1.0
Enhanced Programmable Boot Block
enabling eXecute In Place (XIP)
functionality using 16-bit interface
Small form factors:
512Mb (64MB) capacity (single die):
Enhanced performance by implementation
of:
Unrivaled data integrity with a robust Error
Detection Code/Error Correction Code
(EDC/ECC) tailored for MLC NAND flash
technology
Maximized flash endurance with TrueFFS
6.1 (and higher)
Support for major mobile operating systems
(OSs), including Symbian OS, Pocket PC
2002/3, Smartphone 2002/3, Palm OS,
Nucleus, Linux, Windows CE, and more.
Compatible with major mobile CPUs,
including TI OMAP, XScale, Motorola
DragonBall MX1 and Qualcomm
MSMxxxx.
48-pin TSOP-I package
85-ball FBGA 7x10 mm package
1Gb (128MB) capacity (dual die):
69-ball FBGA 9x12 mm package
Multi-plane operation
DMA support
MultiBurst operation
Turbo operation
Preliminary Data Sheet, June 2003
91-SR-011-05-8L
®

Related parts for MD4331-d1G-MECH

MD4331-d1G-MECH Summary of contents

Page 1

Mobile DiskOnChip G3 512Mbit/1Gbit Flash Disk with MLC NAND and M-Systems’ x2 Technology Highlights Mobile DiskOnChip G3 is one of the industry’s most efficient storage solutions, using Toshiba’s 0.13 µm Multi-Level Cell (MLC) NAND flash technology and x2 technology from ...

Page 2

Performance MultiBurst read: 80 MB/sec Erase: 30 MB/sec Sustained read: 5 MB/sec Sustained write: 1.1 MB/sec Access time: Normal: 55 nsec Turbo: 33 nsec MultiBurst: 25 nsec Protection & Security-Enabling Features 16-byte Unique Identification (UID) number 6KByte user-controlled One Time ...

Page 3

TrueFFS Software Full hard-disk read/write emulation for transparent file system management Patented TrueFFS Flash file system management Automatic block management Data management to maximize the limit of typical flash life expectancy Dynamic virtual mapping Dynamic and static wear-leveling Programming, ...

Page 4

T C ABLE OF ONTENTS 1. Introduction ............................................................................................................................... 5 2. Product Overview ...................................................................................................................... 6 2.1 Product Description ............................................................................................................ 6 2.2 512Mb Standard Interface .................................................................................................. 7 2.2.1 Pin/Ball Diagrams................................................................................................................. 7 2.2.2 System Interface .................................................................................................................. 9 2.2.3 Signal Description .............................................................................................................. 10 2.3 ...

Page 5

Data Pipeline .................................................................................................................... 33 3.9 Control and Status............................................................................................................ 33 3.10 Flash Architecture............................................................................................................. Technology ......................................................................................................................... 36 4.1 MultiBurst Operation......................................................................................................... 36 4.2 DMA Operation................................................................................................................. 38 4.3 Combined MultiBurst Mode and DMA Operation ............................................................. 39 4.4 Turbo Operation ............................................................................................................... ...

Page 6

DiskOnChip Control Register/Control Confirmation Register ........................................... 54 8.9 Device ID Select Register................................................................................................. 55 8.10 Configuration Register...................................................................................................... 55 8.11 Interrupt Control Register ................................................................................................. 56 8.12 Interrupt Status Register................................................................................................... 57 8.13 Output Control Register.................................................................................................... 58 8.14 DPD Control Register ....................................................................................................... 59 ...

Page 7

Product Specifications ........................................................................................................... 76 11.1 Environmental Specifications ........................................................................................... 76 11.1.1 Operating Temperature ...................................................................................................... 76 11.1.2 Thermal Characteristics ..................................................................................................... 76 11.1.3 Humidity.............................................................................................................................. 76 11.1.4 Endurance .......................................................................................................................... 76 11.2 Electrical Specifications.................................................................................................... 76 11.2.1 Absolute Maximum Ratings................................................................................................ 76 11.2.2 Capacitance........................................................................................................................ 77 11.2.3 ...

Page 8

I NTRODUCTION This data sheet includes the following sections: Section 1: Overview of data sheet contents Section 2: Product overview, including a brief product description, ball diagrams and signal descriptions Section 3: Theory of operation for the major building ...

Page 9

P O RODUCT VERVIEW 2.1 Product Description Mobile DiskOnChip G3 is the latest addition to M-Systems’ DiskOnChip product family. Mobile DiskOnChip G3, packed in the smallest available FBGA package with 512Mb (64MB) capacity single-die device with an ...

Page 10

Standard Interface 2.2.1 Pin/Ball Diagrams See Figure 1 and Figure 2 for the Mobile DiskOnChip G3 512Mb pinout/ballout for the standard interface. To ensure proper device functionality, pins/balls marked RSRVD are reserved for future use and should not ...

Page 11

FBGA Package A0/ G VSS DPD H CE# OE# J RSRVD ...

Page 12

System Interface See Figure 3 for a simplified I/O diagram for a standard interface of Mobile DiskOnChip G3 512Mb. CE#, O E#, WE# Host System Bus System Interface Figure 3: Standard Interface Simplified I/O Diagram (Mobile DiskOnChip G3 512Mb) ...

Page 13

Signal Description Mobile DiskOnChip G3 TSOP-I and FBGA packages support identical signals. The related pin and ball designations are listed in the signal descriptions, presented in logic groups, in Table 1 and Table 2. TSOP-I Package Table 1: Signal ...

Page 14

Signal Pin No. DMARQ# 21 IRQ# 47 DPD 19 VCC 12 VCCQ 37 VSS 13, 25, 36, 48 RSRVD 20 The following abbreviations are used Standard (non-Schmidt) input Schmidt Trigger input Open drain output, ...

Page 15

FBGA Package Table 2: Signal Descriptions for Standard Interface (Mobile DiskOnChip 512Mb G3 7x10 FBGA Package) Signal Ball No. A[12:11] D7, C7 A[10:8] F6, E6, C6 A[7:4] C2, D2, E2, F2 A[3:0] D1, E1, F1, G1 D[15:14] H7, K7 ...

Page 16

Signal Ball No. IRQ# F8 DPD G1 VCC J4 VCCQ J5 VSS G2, J8 RSRVD See Figure The following abbreviations are used Standard (non-Schmidt) input Schmidt Trigger input Open drain output, ...

Page 17

Standard Interface 2.3.1 Ball Diagram See Figure 4 for the Mobile DiskOnChip G3 1Gb standard interface ballout. To ensure proper device functionality, balls marked RSRVD are reserved for future use and should not be connected. Note: Mobile DiskOnChip ...

Page 18

System Interface See Figure 5 for a simplified I/O diagram for a standard interface of Mobile DiskOnChip G3 1Gb. CE#, O E#, WE# Host System Bus System Interface Figure 5: Standard Interface Simplified I/O Diagram (Mobile DiskOnChip G3 1Gb) ...

Page 19

Signal Description 9x12 FBGA Package Table 3: Signal Descriptions for Standard Interface (Mobile DiskOnChip G3 1Gb 9x12 FBGA Package) Signal Ball No. A[12:11] D8, C8 A[10:8] F7, E7, C7 A[7:4] C3, D3, E3, F3 A[3:0] D2, E2, F2, G2 ...

Page 20

Signal Ball No. IRQ# F9 DPD G2 VCC J5 VCCQ J6 VSS G3, J9 RSRVD See Figure The following abbreviations are used Standard (non-Schmidt) input Schmidt Trigger input Open drain output, ...

Page 21

Multiplexed Interface 2.4.1 Pin/Ball Diagram See Figure 6 and Figure 7 for the Mobile DiskOnChip G3 512Mb pinout/ballout for the multiplexed interface. To ensure proper device functionality, pins/balls marked RSRVD are reserved for future use and should not ...

Page 22

FBGA Package VSS D VSS VSS E VSS VSS F VSS VSS G DPD VSS H CE# OE# J RSRVD AD0 K AD8 ...

Page 23

System Interface See Figure 8 for a simplified I/O diagram. Host System Bus Figure 8: Multiplexed Interface Simplified I/O Diagram 20 CE#, OE#, WE# Mobile DiskOnChip G3 AD[15:0] ID0 AVD# LOCK# System Interface Configuration Data Sheet, Rev. 1.0 Mobile ...

Page 24

Signal Description Mobile DiskOnChip G3 512Mb TSOP-I and 7x10 FBGA packages support identical signals in the multiplexed interface. The related pin/ball designations are listed in the signal descriptions, presented in logic groups, in Table 4 and Table 5. TSOP-I ...

Page 25

Input Signal Pin No. Type VCCQ 37,22 - VCC 12 - VSS 5-11, 14-18, - 13, 25, 36, 48 RSRVD 20 - The following abbreviations are used Standard (non-Schmidt) input Schmidt Trigger input Open ...

Page 26

FBGA Package Table 5: Signal Descriptions for Multiplexed Interface (Mobile DiskOnChip G3 7x10 FBGA Package) Input Signal Ball No. Type AD[15:14] H7 Multiplexed bus. Address and data signals AD[13:12] H6, J6 AD[11:9] K4, J3, H3 AD[8:6] K2, ...

Page 27

Input Signal Ball No. Type VCC J4 - VCCQ J5 VSS G2,J8, - D7,C7,F6,E6, C6,C2,D2,E2 ,F2,D1,E1,F1 RSRVD See Figure The following abbreviations are used Standard (non-Schmidt) input Schmidt Trigger ...

Page 28

Multiplexed Interface 2.5.1 Ball Diagram See Figure 9 for the Mobile DiskOnChip G3 1Gb (dual-die) ball diagram. To ensure proper device functionality, balls marked RSRVD are reserved for future use and should not be connected. Note: Mobile DiskOnChip ...

Page 29

System Interface See Figure 10 for a simplified I/O diagram. Host System Bus Figure 10: Multiplexed Interface Simplified I/O Diagram 26 CE#, OE#, WE# Mobile DiskOnChip G3 1Gb AD[15:0] LOCK# ID0 AVD# System Interface Configuration Data Sheet, Rev. 1.0 ...

Page 30

Signal Description 9x12 FBGA Package Table 6: Signal Descriptions for Multiplexed Interface (Mobile DiskOnChip G3 1Gb 9x12 FBGA Package) Input Signal Ball No. Type AD[15:14] H8 Multiplexed bus. AD[13:12] H7, J7 AD[11:9] K5, J4, H4 AD[8:6] K3, ...

Page 31

Input Signal Ball No. Type VCC J5 - VCCQ J6 VSS G3,J9, - D8,C8,F7,E7, C7,C3,D3,E3 ,F3,D2,E2,F2 RSRVD See Figure The following abbreviations are used Standard (non-Schmidt) input Schmidt Trigger ...

Page 32

T O HEORY OF PERATION 3.1 Overview Mobile DiskOnChip G3 consists of the following major functional blocks, as shown in Figure 11. *ADDR[0] and DPD are multiplexed on the same ball/pin. Figure 11: Mobile DiskOnChip G3 Simplified Block Diagram, ...

Page 33

Bus Control for translating the host bus address, and data and control signals into valid NAND flash signals. • Address Decoder to enable the relevant unit inside the DiskOnChip controller, according to the address range received from the system ...

Page 34

Mobile DiskOnChip G3 1Gb cannot be cascaded when used in a multiplexed interface). 3.3 Configuration Interface The Configuration Interface block enables the designer to configure Mobile DiskOnChip G3 to operate in different modes. The ID[1:0] ...

Page 35

One-Time Programmable (OTP) Area The 6KB OTP area is user programmable for complete customization. The user can write to this area ...

Page 36

Download Engine (DE) Upon power-up or when the RSTIN# signal is asserted, the DE automatically downloads the Initial Program Loader (IPL) to the Programmable Boot Block. The IPL is responsible for starting the booting process. The download process is ...

Page 37

Flash Architecture Mobile DiskOnChip G3 512Mb consists of two 256Mb flash planes that consist of 1024 blocks each, organized in 64 pages, as follows: • Page – Each page contains 512 bytes of user data and a 16-byte extra ...

Page 38

Good Unit Good Unit Good Unit Bad Unit ~ ~ Good Unit Good Unit Good Unit Flash Plane 1 35 Internal Bus Aligned Unit Aligned Unit Aligned Unit ~ ~ ~ ~ Aligned Unit Aligned Unit Figure 14: Unaligned Multi-Plane ...

Page 39

T X ECHNOLOGY Mobile DiskOnChip G3 enhances performance using various proprietary techniques: • Parallel access to the separate 256Mb flash planes, thereby providing an internal 32-bit data bus. See Section 3.10 for further information. • MultiBurst operation to ...

Page 40

Host Internal data transfers /Flash_OE Data transfer from Flash Planes to FIFO External data transfers /DiskOnChip_OE Data transfer from FIFO to Host Note: Mobile DiskOnChip G3 does not support MultiBurst write operations. MultiBurst operation is controlled by 5 ...

Page 41

The LATENCY bit is the third bit that must be set in the MultiBurst Mode Control register. When the LATENCY bit is set to 0, the host can latch the first 16-bit data word two clock cycles after CLK0. This ...

Page 42

Set the bits in the Interrupt Control register (see Section 8) to enable interrupts on an ECC error and at the end of the DMA operation. 3. Write to the DMA Control register[0] to set the DMA_EN bit, the ...

Page 43

H P ARDWARE ROTECTION 5.1 Method of Operation Mobile DiskOnChip G3 enables the user to define two partitions that are protected (in hardware) against any combination of read or write operations. The two protected areas can be configured as ...

Page 44

Low-Level Structure of the Protected Area The first five blocks in Mobile DiskOnChip G3 contain foundry information, the Data Protect structures, IPL code, and bad block mapping information. See Figure 16. Bad Block Table and Factory-Programmed UID Data Protect ...

Page 45

Block 3 and 4 o Data Protect Structure 1. This structure contains configuration information on one of the two user-defined protected partitions. o IPL Code (2KB). This is the boot code that is downloaded by the DE to the internal ...

Page 46

M O ODES OF PERATION Mobile DiskOnChip G3 operates in one of three basic modes: • Normal mode • Reset mode • Deep Power-Down mode The current mode of the chip can always be determined by reading the DiskOnChip ...

Page 47

Normal Mode This is the mode in which standard operations involving the flash memory are performed. Normal mode is entered when a valid write sequence is sent to the DiskOnChip Control register and Control Confirmation register. The boot detector ...

Page 48

Applications that use Mobile DiskOnChip boot device must ensure that the device is not in Deep Power-Down mode before reading the Boot vector/instructions. This can be done by pulsing RSTIN# to the asserted state and waiting for ...

Page 49

T FFS T RUE ECHNOLOGY 7.1 General Description M-Systems’ patented TrueFFS technology was designed to maximize the benefits of flash memory while overcoming inherent flash limitations that would otherwise reduce its performance, reliability and lifetime. TrueFFS emulates a hard ...

Page 50

Built-In Operating System Support The TrueFFS driver is integrated into all major OSs, including Symbian, Palm OS, Pocket PC 2002/3, Smartphone 2002/3, Windows CE/NT, Linux (various kernels), Nucleus, and others. For a complete listing of all available drivers, please ...

Page 51

To overcome this inherent deficiency, TrueFFS uses M-Systems’ patented wear-leveling algorithm. This wear-leveling algorithm ensures that consecutive writes of a specific sector are not written physically to the same page in the flash. This spreads flash media usage evenly across ...

Page 52

Special Features Through I/O Control (IOCTL) Mechanism In addition to standard storage device functionality, the TrueFFS driver provides extended functionality. This functionality goes beyond simple data storage capabilities to include features such as: formatting the media, read/write protection, boot ...

Page 53

R D EGISTER ESCRIPTIONS This section describes various Mobile DiskOnChip G3 registers and their functions, as listed in Table 7. Most Mobile DiskOnChip G3 registers are 8-bit, unless otherwise denoted as 16-bit. Address (Hex) 103E 1000/1074 1004 1006 1008 ...

Page 54

No Operation (NOP) Register Description: A call to this 16-bit register results in no operation. To aid in code readability and documentation, software should access this register when performing cycles intended to create a time delay. Address (hex): 103E ...

Page 55

Bus Lock Register Description: This register provides a mechanism for a CPU to request and hold sole access rights to Mobile DiskOnChip G3 in multiprocessor applications. The following algorithm must be implemented to ensure that only one CPU at ...

Page 56

Endian Control Register Description: This 16-bit register is used to control the swapping of the low and high data bytes when reading or writing with a 16-bit host. This provides an Endian- independent method of enabling/disabling the byte swap ...

Page 57

DiskOnChip Control Register/Control Confirmation Register Description: These two registers are identical and contain information about the Mobile DiskOnChip G3 operational mode. After writing the required value to the DiskOnChip Control register, the complement of that data byte must also ...

Page 58

Device ID Select Register Description cascaded configuration, this register controls which device provides the register space. The value of bits ID[0:1] is compared to the value of the ID configuration input pins/balls. The device whose ID input ...

Page 59

Interrupt Control Register Description: This 16-bit register controls how interrupts are generated by Mobile DiskOnChip G3, and indicates which of the following five sources has asserted an interrupt: 0: Flash array is ready 1: Data protection violation 2: Reading ...

Page 60

Bit No. 14 EDGE. Selects edge or level triggered interrupts: 0: Specifies level-sensitive interrupts in which the IRQ# output remains asserted until the interrupt is cleared. 1: Specifies edge-sensitive interrupts in which the IRQ# output pulses low and return to ...

Page 61

Output Control Register Description: This register controls the behavior of certain output signals. This register is reset by a hardware reset, not by entering Reset mode. Note: When multiple devices are cascaded, writing to this register will affect all ...

Page 62

DPD Control Register Description: This register specifies the behavior of the DPD input signal. Address (hex): 107C Bit 7 Bit 6 Read/Write Description PD_OK Reset Value 0 Bit No. 3-0 MODE[0:3]. Controls the behavior of the DPD input: 0000: ...

Page 63

DMA Control Register [1:0] Description: These two 16-bit registers specify the behavior of the DMA operation. Address (hex): 1078/107A Bit 7 Bit 6 Read/Write R Description RFU_0 Reset Value 0 Bit 15 Bit 14 Read/Write R Description DMA_EN PAUSE ...

Page 64

Read/Write Description Reset Value 0 Bit No. 9-0 NEGATE_COUNT. When the EDGE bit of DMA Control register[ this bit must be programmed to specify the bus cycle in which DMARQ# will be negated as follows: NEGATE_COUNT = ...

Page 65

MultiBurst Mode Control Register Description: This 16-bit register controls the behavior of Mobile DiskOnChip G3 during MultiBurst mode read cycles. Address (hex): 101C Bit 7 Bit 6 Read/Write Description Reset Value 0 Bit 15 Bit 14 Read/Write Description Reset ...

Page 66

B M OOTING FROM OBILE 9.1 Introduction Mobile DiskOnChip G3 can function both as a flash disk and as the system boot device. Mobile DiskOnChip G3 default firmware contains drivers to enable it to perform as the OS boot ...

Page 67

Mobile DiskOnChip G3 can be used as the only disk in the system, with or without a floppy drive, and with or without hard disks. The drive letter assigned depends on how Mobile DiskOnChip G3 is ...

Page 68

Non-PC Architectures In non-PC architectures, the boot code is executed from a boot ROM, and the drivers are usually loaded from the storage device. When using Mobile DiskOnChip G3 as the system boot device, the CPU fetches the first ...

Page 69

D C ESIGN ONSIDERATIONS 10.1 General Guidelines A typical RISC processor memory architecture is shown in Figure 21. It may include the following devices: • Mobile DiskOnChip G3: Contains the OS image, applications, registry entries, back-up data, user files ...

Page 70

Standard NOR-Like Interface Mobile DiskOnChip G3 uses a NOR-like interface that can easily be connected to any microprocessor bus. With a standard interface, it requires 13 address lines, 8 data lines and basic memory control signals (CE#, OE#, WE#), ...

Page 71

Multiplexed Interface With a multiplexed interface, Mobile DiskOnChip G3 requires the signals shown in Figure 23 below. 0.1 uF Address/Data AVD# Output Enable Write Enable Chip Enable Reset Chip ID 10.4 Connecting Control Signals 10.4.1 Standard Interface When using ...

Page 72

Chip Identification (ID[1:0]) – Connect these signals as shown in Figure 22. Both signals must be connected to VSS if the host uses only one DiskOnChip. If more than one device is being used, refer to Section 10.6 for ...

Page 73

Implementing the Interrupt Mechanism 10.5.1 Hardware Configuration To configure the hardware for working with the interrupt mechanism, connect the IRQ# pin/ball to the host interrupt input. Note: A nominal 10 KΩ pull-up resistor must be connected to this pin/ball. ...

Page 74

Device Cascading When connecting Mobile DiskOnChip G3 512Mb using a standard interface four devices can be cascaded with no external decoding circuitry. Figure 24 illustrates the configuration required to cascade four devices on the host bus (only ...

Page 75

Boot Replacement A typical RISC architecture uses a boot ROM for system initialization. The boot ROM is also required to access Mobile DiskOnChip G3 during the boot sequence in order to load OS images and the device drivers. M-Systems’ ...

Page 76

Platform-Specific Issues Following is a description of hardware design issues for major embedded RISC processor families. 10.8.1 Wait State Wait states can be implemented only when Mobile DiskOnChip G3 is designed in a bus that supports a Wait state ...

Page 77

Data Access Mode When configured for 8-bit operation, pin/ball IF_CFG should be connected to VSS, and data lines D[15:8] are internally pulled up and may be left unconnected. The controller routes odd and even address accesses to the ...

Page 78

Design Environment Mobile DiskOnChip G3 provides a complete design environment consisting of: • Evaluation boards (EVBs) for enabling software integration and development with Mobile DiskOnChip G3, even before the target platform is available. • Programming solutions: o GANG programmer ...

Page 79

P S RODUCT PECIFICATIONS 11.1 Environmental Specifications 11.1.1 Operating Temperature Commercial temperature range: Extended temperature range: -40°C to +85°C 11.1.2 Thermal Characteristics Junction to Case (θ 11.1.3 Humidity 10% to 90% relative, non-condensing 11.1.4 Endurance Mobile DiskOnChip G3 is ...

Page 80

Capacitance Symbol Parameter Input capacitance (512Mb device Input capacitance (1Gb device) Output capacitance (512Mb device) C OUT Output capacitance (1Gb device) Capacitance is not 100% tested. 11.2.3 DC Electrical Characteristics Over Operating Range See Table 12 and ...

Page 81

Table 13: DC Characteristics, VCCQ = 2.5V-3.6V Symbol Parameter VCC Core supply voltage VCCQ Input/Output supply voltage V High-level input voltage IH V Low-level input voltage IL Maximum high level output I OHmax current Maximum low-level output I OLmax current ...

Page 82

AC Operating Conditions Timing specifications are based on the conditions defined below. Parameter Ambient temperature (TA) Core supply voltage (VCC) Input pulse levels Input rise and fall times Input timing levels Output timing levels Output load 79 Table 14: ...

Page 83

Timing Specifications 11.3.1 Read Cycle Timing Standard Interface t SU A[12:0] CE# t (CE1) HO OE# WE# D[15:0] Figure 27: Standard Interface, Read Cycle Timing t SU A[12:0] CE# t (CE1) HO OE# WE# D[15:0] Figure 28: Standard Interface ...

Page 84

Table 15: Standard Interface Read Cycle Timing Parameters Symbol Description Tsu(A) Address to OE# Tho(A) OE# to Address hold time Tsu(CE0) CE# to OE# setup time Tho(CE0) OE# to CE# hold time Tho(CE1) OE# or WE# to CE# Tsu(CE1) CE# ...

Page 85

Write Cycle Timing Standard Interface t SU A[12:0] t (CE1) HO CE# OE# WE# D[15:0] Figure 29: Standard Interface Write Cycle Timing Table 16: Standard Interface Write Cycle Parameters Symbol Description T (A) Address to WE# SU Tho(A) WE# ...

Page 86

Read Cycle Timing Multiplexed Interface AVD# t (AVD) SU AD[15:0] CE# t (CE1) HO OE# WE# Figure 30: Multiplexed Interface Read Cycle Timing Table 17: Multiplexed Interface Read Cycle Parameters Symbol Description tsu(AVD) Address to AVD# tho(AVD) Address to ...

Page 87

Write Cycle Timing Multiplexed Interface AVD# t (AVD) SU AD[15:0] t (CE1) HO CE# OE# WE# Figure 31: Multiplexed Interface Write Cycle Timing Table 18: Multiplexed Interface Write Cycle Parameters Symbol Description tsu(AVD) Address to AVD# tho(AVD) Address to ...

Page 88

Read Cycle Timing MultiBurst In Figure 32, the MultiBurst Control register values are: LATENCY=0, LENGTH=4, CLK_INV=0. t (CLK1) W CLK t (OE0-CLK0) HO OE# t (OE0-CLK1 (OE0-CLK1) SU D[15:0] (HOLD=0) D[15:0] (HOLD=1) Insert LATENCY clock cycles Note: ...

Page 89

Symbol OE 1,3 driven t (D) OE Hi-Z delay HIZ 1. CE# may be asserted any time before or after OE# is asserted. If CE# is asserted after OE#, all timing relative to OE# asserted will ...

Page 90

VCC = 2.5V VCCQ = 1.65 or 2.5V VCC RSTIN# BUSY# A[12:0] CE#, OE# (WE (Read cycle) AVD# (Muxed Mode Only) DPD (A[0]) Symbol T (VCC-RSTIN) VCC/VCCQ stable to RSTIN# REC T (RSTIN) RSTIN# asserted pulse width ...

Page 91

Interrupt Timing IRQ# Symbol Tw(IRQ#) IRQ# asserted pulse width (Edge mode) 11.3.9 DMA Request Timing OE#/CE# DMARQ# Note: Polarity of DMARQ# may be inverted based on the NORMAL bit of DMA Control Register[0]. Symbol Tw(DMARQ#) DMARQ# asserted pulse width ...

Page 92

Mechanical Dimensions 11.4.1 Mobile DiskOnChip G3 512Mb TSOP-I dimensions: 20.0±0. 12.0±0. 1.1±0.10 mm Figure 36: Mechanical Dimensions TSOP-I Package 89 Data Sheet, Rev. 1.0 Mobile DiskOnChip G3 91-SR-011-05-8L ...

Page 93

FBGA dimensions: 7.0±0. 10.0±0. 1.2±0.1 mm Ball pitch: 0.8 mm Figure 37: Mechanical Dimensions 7x10 FBGA Package 90 Data Sheet, Rev. 1.0 Mobile DiskOnChip G3 91-SR-011-05-8L ...

Page 94

Mobile DiskOnChip G3 1Gb (Dual-Die) FBGA dimensions: 9.0±0. 12.0±0. 1.4±0.1 mm Ball pitch: 0.8 mm 9.0 12.0 Figure 38: Mechanical Dimensions 9x12 FBGA Package 91 1.2/ 0.90 1.4 0.33±0. 0.47±0.05 ...

Page 95

... Refer to Table 23 for combinations currently available and the associated order numbers. Ordering Code MD4811-d512-V3Q18 MD4811-d512-V3Q18-X MD4811-d512-V3Q18-P MD4811-d512-V3Q18-X-P MD4832-d512-V3Q18-X MD4832-d512-V3Q18-X-P MD4331-d1G-V3Q18-X MD4331-d1G-V3Q18-X-P MD3831-d00-DAISY MD4832-d00-DAISY MD4811-d512-MECH MD4832-d512-MECH MD4331-d1G-MECH 92 MDxxxx-Dxxx-xxx-T-C Capacity D- MByte d- Mbit xxx - Value Supply Voltage V3Q18 - 3.3V core, 1.8V I/O Figure 39: Ordering Information Structure Table 23: Available Combinations Capacity Package MB ...

Page 96

... ONTACT S USA M-Systems Inc. 8371 Central Ave, Suite A Newark CA 94560 Phone: +1-510-494-2090 Fax: +1-510-494-5545 Japan M-Systems Japan Inc. Asahi Seimei Gotanda Bldg., 3F 5-25-16 Higashi-Gotanda Shinagawa-ku Tokyo, 141-0022 Phone: +81-3-5423-8101 Fax: +81-3-5423-8102 Taiwan M-Systems Asia Ltd. Room No. 133 Sec. 3 ...

Related keywords