MD4331-d1G-MECH M-Systems Inc., MD4331-d1G-MECH Datasheet - Page 72

• Manufacturer Part Number: MD4331-d1G-MECH
• Description: Mobile Diskonchip G3 Data Sheet
• Manufacturer: M-Systems Inc.

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10.4.2 Multiplexed Interface
Mobile DiskOnChip G3 can use a multiplexed interface to connect to the multiplexed bus
(asynchronous read/write protocol). In this configuration, the ID[1] input is driven by the host's
AVD# signal, and the D[15:0] pins/balls, used for both address inputs and data, are connected to the
host AD[15:0] bus. As with a standard interface, only address bits [12:0] are significant.
This mode is automatically entered when a falling edge is detected on ID[1]. This edge must occur
after RSTIN# is negated and before OE# and CE# are both asserted; i.e., the first read cycle made to
DiskOnChip must observe the multiplexed mode protocol. See Section 11.3 for more information
about the related timing requirements.
Please refer to Section 2.4 for pinout and signal descriptions and to Section 11.3 for timing
specifications for a multiplexed interface.
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Chip Identification (ID[1:0]) – Connect these signals as shown in Figure 22. Both signals must
be connected to VSS if the host uses only one DiskOnChip. If more than one device is being
used, refer to Section 10.6 for more information on device cascading.
Busy (BUSY#) – This signal indicates when the device is ready for first access after reset. It
may be connected to an input port of the host, or alternatively it may be used to hold the host in
a wait-state condition. The later option is required for hosts that boot from Mobile DiskOnChip
G3.
DMARQ# (DMA Request) – Output used to control multi-page DMA operations. Connect this
output to the DMA controller of the host platform.
IRQ# (Interrupt Request) – Connect this signal to the host interrupt.
Lock (LOCK#) – Connect to a logical 0 to prevent the usage of the protection key to open a
protected partition. Connect to logical 1 in order to enable usage of protection keys.
Deep-Power Down (DPD) – multiplexed with A[0].
8/16 Bit Interface Configuration (IF_CFG) – This signal is required for configuring the device
for 8- or 16-bit access mode. When negated, the device is configured for 8-bit access mode.
When asserted, 16-bit access mode is operative.
Clock (CLK) – This input is used to support MultiBurst operation when reading flash data.
Refer to Section 4.1 for further information on MultiBurst operation.
Data Sheet, Rev. 1.0
Mobile DiskOnChip G3
91-SR-011-05-8L