MD4331-d1G-MECH M-Systems Inc., MD4331-d1G-MECH Datasheet - Page 33

• Manufacturer Part Number: MD4331-d1G-MECH
• Description: Mobile Diskonchip G3 Data Sheet
• Manufacturer: M-Systems Inc.

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3.2
3.2.1
The system interface block provides an easy-to-integrate NOR-like (also SRAM and EEPROM-
like) interface to Mobile DiskOnChip G3, enabling it to interface with various CPU interfaces, such
as a local bus, ISA bus, NOR interface, SRAM interface, EEPROM interface or any other
compatible interface. In addition, the EEPROM-like interface enables direct access to the
Programmable Boot Block to permit XIP (Execute-In-Place) functionality during system
initialization.
A 13-bit wide address bus enables access to the Mobile DiskOnChip G3 8KB memory window (as
shown in Section 7.2). A 16-bit internal data bus is supported by parallel access to two 256Mb flash
planes (for 512Mb single-die devices), each of which enables 8-bit access. This 16-bit data bus
permits 16-bit wide access to the host.
The Chip Enable (CE#), Write Enable (WE#) and Output Enable (OE#) signals trigger read and
write cycles. A write cycle occurs while both the CE# and the WE# inputs are asserted. Similarly, a
read cycle occurs while both the CE# and OE# inputs are asserted. Note that Mobile DiskOnChip
G3 does not require a clock signal. It features a unique analog static design, optimized for minimal
power consumption. The CE#, WE# and OE# signals trigger the controller (e.g., system interface
block, bus control and data pipeline) and flash access.
The Reset In (RSTIN#) and Busy (BUSY#) control signals are used in the reset phase.
The Interrupt Request (IRQ#) signal can be used when long I/O operations, such as Block Erase,
delay the CPU resources. The signal is also asserted when a Data Protection violation has occurred.
This signal frees the CPU to run other tasks, continuing read/write operations with Mobile
DiskOnChip G3 only after the IRQ# signal has been asserted and an interrupt handling routine
(implemented in the OS) has been called to return control to the TrueFFS driver.
The DMARQ# output is used to control multi-page DMA operations, and the CLK input is used to
support MultiBurst operation when reading flash data. See Section 4.1 for further information.
3.2.2
In this configuration, the address and data signals are multiplexed. The ID[1] input is driven by the
host AVD# signal, and the D[15:0] pins/balls, used for both address inputs and data, are connected
to the host AD[15:0] bus. While AVD# is asserted, the host drives AD[11:0] with bits [12:1] of the
address. Host signals AD[15:12] are not significant during this part of the cycle.
This interface is automatically used when a falling edge is detected on ID[1]. This edge must occur
after RSTIN# is negated and before the first read or write cycle to the controller. When using a
multiplexed interface, the value of ID[1] is internally forced to logic-0. The only possible device ID
values are 0 and 1; therefore, only up to two Mobile DiskOnChip G3 512Mb devices may be
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Bus Control for translating the host bus address, and data and control signals into valid NAND
flash signals.
Address Decoder to enable the relevant unit inside the DiskOnChip controller, according to
the address range received from the system interface.
System Interface
Standard (NOR-Like) Interface
Multiplexed Interface
Data Sheet, Rev. 1.0
Mobile DiskOnChip G3
91-SR-011-05-8L