AD9957 Analog Devices, AD9957 Datasheet - Page 16

• Manufacturer Part Number: AD9957
• Description: 1 GSPS Quadrature Digital Upconverter
• Manufacturer: Analog Devices

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DataSheet
AD9957
two outputs. The use of balanced outputs reduces the amount of
common-mode noise at the DAC output, increasing signal-to-
noise ratio. An external resistor (R
DAC_R
a reference current. The full-scale output current of the DAC
(I
(see the Auxiliary DAC section that follows).
Proper attention should be paid to the load termination to keep the
output voltage within the specified compliance range, as voltages
developed beyond this range will cause excessive distortion and
might even damage the DAC output circuitry.
Auxiliary DAC
The full scale output current of the main DAC (I
trolled by an 8-bit auxiliary DAC. An 8-bit code word stored in
As in the quadrature modulation mode, the PDCLK pin func-
tions as a clock which serves to synchronize the input of data to
the AD9957. The PDCLK rate is given below. Note that it oper-
ates at a rate that is half of that for the quadrature modulation
mode.
Because no modulation takes place, the spectrum of the data
supplied at the parallel port remains at base band. However, a
sample rate conversion takes place based on the programmed
f
OUT
DATA
PDClk
I/Q In
TxEn
4
) is produced as a scaled version of the reference current
U
=
SET
.com
f
SYSCLK
4
pin and the DAC ground (AGND_DAC) establishes
18
R
Programming
Parallel Data
Registers
3
Timing &
Control
(Interpolating DAC mode)
I
Q
I
0
1
1
0
CCI
CCI
Inv.
Inv.
2
Serial I/O
Port
SET
Halfband
Halfband
) connected between the
Filters
Filters
(4x)
(4x)
Internal Clock Timing & Control
AD9957: Interpolating DAC Mode
I
(1x -63x)
(1x -63x)
Q θ
RAM
CCI
CCI
OUT
G
R
F
Figure 11: Interpolating DAC Mode
) is con-
F
PW
1
0
R
θ
Rev. PrF | Page 16 of 38
FTW
1
0
Ramp
Logic
Freq.
Control
Power
Down
θ
ω
DDS
cos(ωt+θ)
sin(ωt+θ)
the appropriate register map location sets I
following equation:
Where R
is the 8-bit value supplied to the auxiliary DAC (default is 127).
For example, with R
I
INTERPOLATING DAC MODE
A block diagram of the AD9957 operating in the interpolating
DAC mode is shown in Figure 11; grayed out items are inactive.
In this mode, the Q data path, DDS and modulator are all dis-
abled; only the I data path is active.
interpolation rate. The interpolation hardware processes the
signal, by effectively performing an over-sample with zero-
stuffing operation. However, the original input spectrum re-
mains intact and the images that would otherwise occur from
the sample rate conversion process are suppressed by the inter-
polation signal chain.
The PDCLK pin is an output and serves as a data clock timing
source. The output clock rate is f
Data Assembler section. Each PDCLK rising edge latches a data
word into the I data path.
I
2
OUT
OUT
2
=20.07mA.
=
86
R
3
1
0
2
SET
SET
4 .
is the value of the R
0
1
⎛
⎜
⎝
PRELIMINARY TECHNICAL DATA
1
sin(x)
+
DAC
Gain
Multiplier
x
CODE
Clock
96
SET
8
=10,000 and CODE=127, then
⎞
⎟
⎠
OSF
0
1
AUX
DAC
(8-b)
0
1
2
SET
2
DATA
resistor (in ohms) and CODE
DAC
(14-b)
as explained in the Input
OUT
according to the
RefClk
RefClk
DAC
Rset
Iout
Iout
(6)