AD9957 Analog Devices, AD9957 Datasheet - Page 36

• Manufacturer Part Number: AD9957
• Description: 1 GSPS Quadrature Digital Upconverter
• Manufacturer: Analog Devices

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DataSheet
AD9957
CFR3<0> :
Auxilliary DAC Control Register
These 8 bits control the auxiliary DAC that modulates the full
scale current of the Tx DAC. For a default DAC_Rset value of
10K, these bits modulate the DAC output full scale current be-
tween 8.66mA and 31.66mA, with each LSB representing ap-
proximately 90μA of resolution.
IO Update Rate Register
This register sets the interval for the down counter which di-
vides the system clock down to an internal I/O update interval
period. When the internal I/O Update mode is disabled, this
register is ignored. Each LSB represents one SYNC_CLK cycle,
so the interval for an internal I/O update rate varies between 1
and 2^32( 4,294,967,296) sync_clock cycles, where a sync_clock
cycle is ¼ of a system clock cycle.
QDUC RAM Segment Registers (QRSR0, QRSR1)
These registers program the behavior of the internal RAM con-
troller for when the RAM is configured to drive QDUC data or
drive the input scalars. QRSR0 feeds data to the I-channel and
QRSR1 feeds data to the Q-channel. These registers serve no
function when the AD9957 is programmed to be in single-tone
mode.
QRSRX<47:32> RAM Segment Address Ramp Rate
QRSRX<31:22> RAM Segment Final Address
QRSRX<21:16> OPEN
QRSRX<15:6> RAM Segment Beginning Address
QRSRX<5:3> OPEN
QSRX<2:0> RAM Segment Mode Control
4
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ble 4). If the PLL is enabled (CFR3<8>), a valid value must
be programmed here for proper PLL operation. If the PLL
is disabled, these bits are ignored.
When CFR3<0>= 0 (default) the reference clock is fed di-
rectly to the PFD.
When CFR3<0> = 1, the reference clock is doubled in fre-
quency prior to being fed to the PFD.
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This 16 bit word controls the period between QDUC
RAM segment steps. Each LSB in this word weights
the delay by 1 SYNC_CLK cycle (which is ¼ the sys-
tem clock rate).
This 10 bit word specifies the final address location in
the RAM where the data profile is stored.
This 10 bit word specifies the beginning address loca-
tion in the RAM where the data profile is stored.
REFCLK input doubler active bit
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QSRX<2:0>
000
001
010
011
100
101, 110,
111
Frequency Tuning Word Register (FTW)
This register sets the frequency tuning word of the DDS core,
which is either the output frequency (single tone mode) or the
carrier frequency (modulator mode). When the
Phase/Frequency/Amplitude Profiles are enabled, this register
serves no function.
Phase Offset Word Register (POW)
This register controls the phase offset of the DDS core in either
the output frequency (single tone mode) or the carrier fre-
quency (modulator mode). When the
Phase/Frequency/Amplitude Profiles are enabled, this register
serves no function.
Amplitude Scale Factor (ASF)
This register controls the digital multiplier (amplitude scale
factor) inside the DDS core itself. It does not affect the digital
multiplier immediately prior to the DAC . In automatic OSK
mode, this controls the ramp rate and final value of the ampli-
tude ramping function. In manual OSK mode, only the Ampli-
tude Scale Factor is used, the Amplitude Ramp Rate is ‘don’t
care’ . When the Phase /Frequency /Amplitude Profiles are en-
abled, this register serves no function.
QDUC Profile X Register (QDUC-PXR)/
Single Tone Profile X Register (ST-PXR)
There are 8 special purpose registers which reside at addresses
h’0E to h’15. These registers can take on one of three roles: they
can either be QDUC Profile Registers, RAM Profile Registers or
Single Tone Profile Registers.
This 3 bit word specifies the behavior the RAM con-
troller follows when stepping through the Segment ac-
cording to the following table. Note, the behavior in-
dicated refers to the RAM address itself, not necessar-
ily the data stored and sent to the QDUC.
PRELIMINARY TECHNICAL DATA
RAM Mode
Direct Switch (Beginning Address only)
Ramp Up
Bidirectional Ramp (ramp up, ramp down)
Continuous Bidirectional (ramp up, ramp
down, ramp up, etc)
Continous recirculate (Ramp up from
beginning to final address, then immediately
return to beginning address and repeat).
Not Used