AD9957 Analog Devices, AD9957 Datasheet - Page 32

• Manufacturer Part Number: AD9957
• Description: 1 GSPS Quadrature Digital Upconverter
• Manufacturer: Analog Devices

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DataSheet
AD9957
REGISTER DESCRIPTIONS
Control Function Register #1 (CFR1)
The CFR1 is comprised of four bytes located in address 00h.
CFR1<31> : RAM Enable bit .
CFR1<30:29> : OPEN . Always leave these bits clear.
CFR1<28> : RAM QDUC Evaluation Enable bi t.
CFR1<27:26> : OPEN . Always leave these bits clear.
CFR1<25:24> : QDUC Operating Mode bits .
CFR1<23> : Manual OSK External Control .
CFR1<22> : Inverse Sinc Enable bit .
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When CFR1<31> = 0 (default), disables the RAM putting
it in the lowest power state (unless being written to via
the serial port).
When CFR1<31> = 1, enables the RAM.
When CFR1<28> = 0 (default), The RAM QDUC
evaluation mode of the device is inactive.
When CFR1<28> = 1, The RAM QDUC evaluation
mode is activated, if the RAM Enable bit is set. When in
the RAM QDUC Evaluation mode the input data port is
disengaged form the signal processing path and the
RAM drives the I and Q data at the IQ sample rate.
The CFR1<25:24> bits set the mode of operation:
Note, this bit is ignored unless manual OSK mode is se-
lected using CFR1<9:8>.
When CFR1<23> = 0 (default), the manual OSK mode
does not require the use of the OSK input pin to operate.
When CFR1<23> = 1, the manual OSK mode uses the
OSK input pin. See pin description.
When CFR1<22> = 0 (default), the inverse sinc filter is
inactive - the local clock is stopped to save power. The
input data is passed directly to the output of the filter.
When CFR1<22> = 1, the inverse sinc filter is enabled
and operational.
CFR1<25:24>
.com
00 (default)
01
1x
Mode of Operation
Quadrature Modulation
Single Tone
Interpolating DAC
Rev. PrF | Page 32 of 38
CFR1<21> : Clear CCI bit .
CFR1<20:17> : Internal Profile Control bits .
CFR1<16> : Sine Enable bit .
CFR1<15:14> : OPEN . Always leave these bits clear.
CFR1<13>: Auto Clear Phase Accumulator
CFR1<12>: OPEN . Always leave this bit clear.
CFR1<11>: Clear Phase Accumulator
CFR1<10> : Load Amplitude Rate Register @ IOUpdate
CFR1<9> : Output Shaped Keying Enable
When CFR1<21> = 0 (default), the CCI filter operates
normally.
When CFR1<21> = 1, The CCI filter is asynchronously
cleared.
These bits cause the Profile Bits to be ignored and put
the device into an automatic “profile loop sequence” that
allows the user to implement a frequency/phase compos-
ite sweep that runs without external inputs.
When CFR1<16> = 0 (default), the angle-to-amplitude
conversion logic outputs a COSINE function.
When CFR1<16> = 1, the angle-to-amplitude conver-
sion logic outputs a SINE function.
When CFR1<13> = 0 (default), ), the accumulation
function is not interrupted.
When CFR1<13> = 1, this bit automatically and syn-
chronously clears (loads zeros into) the phase accumula-
tor for one cycle upon receipt of the I/O UPDATE se-
quence indicator.
When CFR1<11> = 0 (default), the phase accumulator
functions as normal.
When CFR1<11> = 1, the phase accumulator memory
element is asynchronously cleared.
When CFR1<10> = 0 (default), the amplitude ramp rate
timer is loaded only upon timeout (timer ==1); it is not
loaded due to an I/O UPDATE input signal (or change
in profile).
When CFR1<10> = 1, the amplitude ramp rate timer is
loaded upon timeout (timer ==1) or at the time of an
I/O UPDATE input signal (or change in profile).
PRELIMINARY TECHNICAL DATA