ADIS16250 Analog Devices, ADIS16250 Datasheet - Page 16

• Manufacturer Part Number: ADIS16250
• Description: Programmable Low Power Gyroscope
• Manufacturer: Analog Devices

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ADIS16250
OPERATIONAL CONTROL
Internal Sample Rate
The internal sample rate defines how often data output variables
are updated, independent of the rate at which they are read out
on the SPI port. The SMPL_PRD register controls the ADIS16250
internal sample rate and has two parts: a selectable time base and
a multiplier. The sample period can be calculated using the
following equation:
The default value is the maximum 256 samples per second, and
the contents of this register are nonvolatile.
Table 15. SMPL_PRD Register Definition
Address
0x37, 0x36
Table 16. SMPL_PRD Bit Descriptions
Bit
15:8
7
6:0
Here is an example calculation of the sample period for the
ADIS16250:
The sample rate setting has a direct impact on the SPI data rate
capability. For sample rates of 64 SPS and above, the SPI SCLK
can run at a rate up to 2.5 MHz. For sample rates below 64 SPS,
the SPI SCLK can run at a rate up to 1 MHz.
The sample rate setting also affects the power dissipation.
When the sample rate is set below 64 SPS, the power dissipation
reduces by a factor of 60%. The two different modes of
operation offer a system-level trade-off between performance
(sample rate, serial transfer rate) and power dissipation.
T
Where:
T
T
N
If SMPL_PRD = 0x0007, B7 − B0 = 00000111
B7 = 0 → T
B6…B0 = 000000111 → N
T
f
S
S
S
B
S
S
= 1∕T
Description
Not used
Time base, 0 = 1.953 ms, 1 = 60.54 ms
Multiplier
= T
= sample period
= time base
= T
= increment setting
B
B
S
× (N
× (N
= 64 SPS
B
Default
0x0001
= 1.953 ms
S
S
+ 1)
+ 1) = 1.953 ms × (7 + 1) = 15.624 ms
S
= 7
Format
N/A
Access
R/W
Rev. 0 | Page 16 of 20
Power Management
In addition to offering two different performance modes for
power optimization, the ADIS16250 offers a programmable
shutdown period. Writing the appropriate sleep time to the
SLP_CNT register shuts the device down for the specified time.
The following example provides an illustration of this
relationship:
After completing the sleep period, the ADIS16250 returns to
normal operation. If measurements are required before sleep
period completion, the ADIS16250 can be awakened by putting
the CS line in a zero logic state. Otherwise, the CS line must be
kept high to maintain sleep mode.
Table 17. SLP_CNT Register Definition
Address
0x3B, 0x3A
1
Table 18. SLP_CNT Bit Descriptions
Bit
15:8
7:0
Analog Bandwidth
The analog bandwidth of the ADIS16250 is 50 Hz. This
bandwidth can be reduced by placing an external capacitor
across the RATE and FILT pins. In this case, the analog
bandwidth can be calculated using the following equation:
Digital Filtering
The ADIS16250 GYRO_OUT signal path has a nominal analog
bandwidth of 50 Hz. The ADIS16250 provides a Bartlett Window
FIR filter for additional noise reduction on all of the output data
registers. The SENS/AVG register stores the number of taps in
this filter in seven, “power of two, ” step sizes (that is, –2
16, 32, 64, and 128). Filter setup requires one simple step: write
the appropriate M factor to the assigned bits in the SENS/AVG
register. The bit assignments are listed in Table 20. The following
equation offers a frequency response relationship for this filter:
Scale is the weight of each LSB.
B7 … B0 = 00000110
Sleep period = 3 seconds
f
R
C
OUT
H
OUT
OUT
B
= 1/(2 × π × R
(
= 45.22 kΩ
= external capacitance
Description
Not used
Data bits
f
)
=
Scale
0.5sec
H
2
A
(
1
f
)
OUT
Default
0x0000
⇒
× (C
H
OUT
A
(
+ 0.068 μF))
f
Format
Binary
)
=
sin
N
×
(
π
sin
×
Access
R/W
(
N
π
×
×
f
f
M
×
×
= 1, 2, 4,
t
t
s
s
)
)