ADIS16250 Analog Devices, ADIS16250 Datasheet - Page 17

• Manufacturer Part Number: ADIS16250
• Description: Programmable Low Power Gyroscope
• Manufacturer: Analog Devices

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Dynamic Range
The ADIS16250 provides three dynamic range settings: ±80°/sec,
±160°/sec, and ±320°/sec. The lower dynamic range settings
(80, 160) limit the minimum filter tap sizes in order to maintain
the resolution as the maximum rate measurements decrease.
The recommended order for programming the SENS/AVG
register is (1) dynamic range and then (2) filtering response.
The contents of the SENS/AVG register are nonvolatile.
Table 19. SENS/AVG Register Definition
Address
0x39, 0x38
Table 20. SENS/AVG Bit Descriptions
Bit
15:11
10:8
7:4
3:0
Auxiliary DAC
The auxiliary DAC provides a 12-bit level adjustment function.
The AUX_DAC register controls the operation of this feature. It
offers a rail-to-rail buffered output that has a range of 0 V to 2.5 V.
The DAC can drive its output to within 5 mV of the ground
reference when it is not sinking current. As the output
approaches ground, the linearity begins to degrade (100 LSB
beginning point). As the sink current increases, the nonlinear
range increases. The DAC output latch function, contained in
the COMMAND register, provides continuous operation while
writing each byte of this register. The contents of this register
are volatile, which means that the desired output level must be
set after every reset and power cycle event.
–100
–120
–140
–160
–20
–40
–60
–80
Value
100
010
001
0.001
0
Figure 23. Bartlett Window FIR Frequency Response
Default
0x0400
Sensitivity selection bits
Description
Not used
320°/sec (default condition)
160°/sec, filter taps ≥ 4 (Bit 3:0 ≥ 0x02)
80°/sec, filter taps ≥16 (Bit 3:0 ≥ 0x04)
Not used
Filter tap setting, M = binary number
(number of taps, N = 2
N = 128
0.01
FREQUENCY (f/fs)
N = 16
Format
Binary
M
N = 4
)
0.1
Access
R/W
N = 2
1
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Table 21. AUX_DAC Register Definition
Address
0x31, 0x30
Table 22. AUX_DAC Bit Descriptions
Bit
15:12
11:0
General-Purpose I/O
The ADIS16250 provides two general-purpose pins that enable
digital I/O control using the SPI. The GPIO_CTRL control
register establishes the configuration of these pins and handles
the SPI-to-pin controls. Each pin provides the flexibility of both
input (read) and output (write) operations. For example, writing
a 0x0202 to this register establishes Line 0 as an output and sets
its level as a one. Writing 0x0000 to this register establishes both
lines as inputs, and their status can be read through Bit 0 and Bit 1
of this register.
The digital I/O lines are also available for data-ready and
alarm/error indications. In the event of conflict, the following
priority structure governs the digital I/O configuration:
Table 23. GPIO_CTRL Register Definition
Address
0x33, 0x32
Table 24. GPIO_CTRL Bit Descriptions
Bit
15:10
9
8
7:2
1
0
•
•
•
Description
Not used
General-purpose I/O line 0, data direction control
General-purpose I/O line 1, data direction control
Not used
General-purpose I/O line 0 polarity
General-purpose I/O line 1 polarity
GPIO_CTRL
MSC_CTRL
ALM_CTRL
1 = output, 0 = input
1 = output, 0 = input
1 = high, 0 = low
1 = high, 0 = low
Description
Not used
Data bits
Default
0x0000
Default
0x0000
Format
N/A
Format
Binary
ADIS16250
Access
R/W
Access
R/W