OPB16450UART Xilinx Corp., OPB16450UART Datasheet - Page 4

• Manufacturer Part Number: OPB16450UART
• Description: Ds433 August 18, 2004 Product Specification
• Manufacturer: Xilinx Corp.

OPB 16450 UART
Table 2: UART I/O Signals (Continued)
Parameter - Port Dependencies
The width of many of the OPB UART signals depends on parameter. In addition, when certain features are parameterized
away, the related input signals are unconnected. The dependencies between the OPB UART design parameters and I/O sig-
nals are shown in
4
UART
Signals
System
Grouping
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
Table
baudoutN
rclk
sin
sout
xin
xout
ctsN
dcdN
dsrN
dtrN
riN
rtsN
ddis
out1N
out2N
rxrdyN
txrdyN
OPB_Clk
OPB_Rst
Freeze
3. parameters and I/O signals are shown in the following table.
Signal Name
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Serial
Serial
Serial
Serial
Serial
Serial
Modem
Modem
Modem
Modem
Modem
Modem
User
User
User
User
User
System
System
System
1-800-255-7778
Interface
I/O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
m State
diagra
Initial
~XIN
1
1
1
1
1
1
1
1
1
Transmitter Clock
Receiver 16x Clock (Optional.
May be driven by baudoutN
under control of the
C_HAS_EXTERNAL_RCLK
parameter).
Serial Data Input
Serial Data Output
Baud Rate Generator reference
clock. (Optional. May be driven
by OPB_Clk under control of the
C_HAS_EXTERNAL_XIN
parameter).
Inverted XIN
ClearToSend (active low)
Data Carrier Detect (active low)
Data Set Ready (active low)
Data Terminal Ready (active
low)
Ring Indicator (active low)
Request To Send (active low)
Driver Disable. Low when CPU
is reading OPB UART
User controlled output
User controlled output
DMA control signal
DMA control signal
System clock
System Reset (active high)
Freezes UART for software
debug (active high)
Description
DS433 August 18, 2004
Product Specification