OPB16450UART Xilinx Corp., OPB16450UART Datasheet - Page 9

• Manufacturer Part Number: OPB16450UART
• Description: Ds433 August 18, 2004 Product Specification
• Manufacturer: Xilinx Corp.

Line Control Register
As shown in
Modem Control Register
As shown in
DS433 August 18, 2004
Product Specification
Table 9: Line Control Register Bit Definitions
Table 10: Modem Control Register Bit Definitions
Location
Location
1-0
7-5
Bit
Bit
7
6
5
4
3
2
4
3
Table
Table
Stick Parity
Set Break
Name
Name
DLAB
9, the Line Control Register contains the serial communication configuration bits.
10, the Modem Control Register contains the modem signaling configuration bits.
Loop
PEN
WLS
Out2
EPS
STB
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Access
Access
Reset Value
Reset Value
“000"
www.xilinx.com
“00”
1-800-255-7778
“0”
“0”
“0”
“0”
“0”
“0”
"0"
"0"
(1)
Divisor Latch Access Bit.
"1" -> Allows access to the Divisor Latch Registers
and reading of the FIFO Control Register.
Set Break.
"1" -> Sets SOUT to "0".
Stick Parity.
"1" -> Forces parity to "1" or "0" based on bits 3 and 4.
Even Parity Select.
1 -> Selects Even parity.
0-> Selects Odd parity.
Parity Enable.
"1" -> Enables parity.
Number of Stop Bits.
"0" -> 1 Stop bit.
"1" -> 2 Stop bits or 1.5 if
5 bits/character selected).
Word Length Select.
"00" -> 5 bits/character.
"01" -> 6 bits/character.
"10" -> 7 bits/character.
"11" -> 8 bits/character.
Loop Back.
"1" -> Enables loop back.
User Output 2.
"1" -> Drives OUT2N low.
"0" -> Drives OUT2N high.
Description
Description
OPB 16450 UART
9