AD9433-105 Analog Devices, AD9433-105 Datasheet

AD9433-105

Manufacturer Part Number

AD9433-105

Description

12-Bit, 105/125 MSPS Analog-to-digital if Sampling Converter

Manufacturer

Analog Devices

Datasheet

1.AD9433-105.pdf (11 pages)

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Preliminary Technical Data

FEATURES

IF Sampling up to 400MHz

IF Mode select for optimized SINAD and SFDR

On Chip Clock Duty Cycle Stabilization

On–chip reference and track/hold

SFDR Optimization circuit

Excellent Linearity:

750 MHz Full Power Analog Bandwidth

SNR = 67dB @ Fin up to Nyquist

SFDR = 85dBc @ Fin up to 125 MHz

SFDR = 80dBc @ Fin up to 250 MHz

THD = 90dBc @ Fin up to 250 MHz

Power dissipation = 1.3W typical at 125Msps

Input voltage of 1Vp-p or 2Vp-p

Two’s complement or Offset binary data format

+5.0V Analog Supply Operation

+2.5V to 3.3V TTL/CMOS outputs.

APPLICATIONS

Wireless and Wired Broadband Communications

Communications Test Equipment

“IF Sampling” schemes

Radar and Satellite sub-systems

GENERAL INTRODUCTION

The AD9433 is a 12-bit monolithic sampling analog–to–

digital converter with an on–chip track–and–hold circuit and

is designed for ease of use. The product operates up to 125

Msps conversion rate and is optimized for outstanding

dynamic performance in wideband and high IF carrier

systems.

The ADC requires a +5V analog power supply and a

differential encode clock for full performance operation.

No external reference or driver components are required for

many applications. The digital outputs are TTL/CMOS

compatible and a separate output power supply pin supports

interfacing with 3.3V or 2.5V logic.

REV. PrD 12/19/2000 10:46 AM

Characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing or

sale of this product. Last Revision TBD. For latest specification e-mail

- Wideband carrier frequency systems

- DNL = +/- 0.25 lsb (typ)

- INL = +/- 0.5 lsb (typ)

PRELIMINARY TECHNICAL DATA

highspeed.converters@analog.com

A user selectable on-chip circuit optimizes SFDR

performance of 90dBc from DC to 70MHz. A user select

allows optimized SINAD vs SFDR for a particular input

frequency range.

The encode clock supports either differential or single-

ended input and is PECL compatible and an output data

format select option of two’s complement or offset binary

are also supported.

Fabricated on an advanced BiCMOS process, the AD9433

is available in a 52 pin surface mount plastic package (52

LQFP) specified over the industrial temperature range (–

40°C to +85°C) and is pin compatible with the AD9432.

AD9433 FUNCTIONAL BLOCK DIAGRAM

IF Sampling A/D Converter

E N C O D E /

E N C O D E

A I N /

A I N

A D 9 4 3 3

12-Bit, 105/125 MSPS

E N C O D E

Analog Devices Preliminary Specification

T I M I N G

T / H

G N D

O U T

R E F

P i p e l i n e

A D C

R E F

V CC

1 2

AD9433

1 2

S F D R

S e l e c t # 1

S e l e c t # 2

D F S

- D

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