TEA0679 NXP Semiconductors, TEA0679 Datasheet - Page 15

• Manufacturer Part Number: TEA0679
• Description: I2c-bus Controlled dual Dolby* B-type Noise Reduction Circuit for Playback Applications
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Description of the principle timing diagram for AMS latch mode with initial input signal (see Fig.8)
This is similar to the description in Section “Description of the principle timing diagram for AMS scan mode with initial
input signal (see Fig.6)”. It only differs in its rise time t
upper threshold between t
The following behaviour does not differ from the description in Section “Description of the principle timing diagram for
AMS latch mode without initial input signal (see Fig.7)”.
1998 Nov 12
handbook, full pagewidth
I
reduction circuit for playback applications
t
2
r
= rise time; t
C-bus controlled dual Dolby* B-type noise
upper threshold
level threshold
time threshold
latch status
to power FET
output signal
(hysteresis)
internal
V AMSEQ
4.5 V
V ref
d
V in
= delay time; t
V t
V l
H
L
AMS on
t 0 t 1
b
0
= burst time; t
and t
t 5 t 6
1
. The initial procedure is now completed.
t f
t d
Fig.8 AMS latch mode with initial input signal.
p
= pause time; t
t 7 t 8 t 9 t 10
t b
t r
f
= fall time.
r
and a release of its internal latch when voltage V
15
t 11 t 12
t 13 t 14
t p
t d
t 15
Product specification
V l : voltage at
pin 8 (CONTRA)
TEA0679T
V t : voltage at
pin 25 (CONTRB)
level detector
input
time detector
input
t
exceeds the
MHB123
t
t
t
t
t