HFC-S+ Cologne Chip AG, HFC-S+ Datasheet - Page 13

• Manufacturer Part Number: HFC-S+
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C
2.6
u)
2.7
(e. g. for PCM codecs)
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Pin No.
85
86
87
88
91
92
internal pull up
GCI/IOM2 bus interface
GCI/IOM2 Timeslot enable signals
C4IO
F0IO
STIO1
STIO2
F1_A
F1_B
Pin Name
Output
Input
I/O
I/O
I/O
I/O
O
O
u)
u)
u)
u)
all
all
all
all
all
all
Mode
Function
4.096 Mhz clock
GCI/IOM2 bus clock master: output
GCI/IOM2 bus clock slave: input (reset default)
Frame synchronisation, 8kHz pulse for GCI/IOM2
bus frame synchronisation
GCI/IOM2 bus master: output
GCI/IOM2 bus slave: input (reset default)
GCI/IOM2 bus databus I
Slotwise programmable as input or output
GCI/IOM2 bus databus II
Slotwise programmable as input or output
enable signal for external CODEC A
Programmable as positive (reset default) or negative
pulse.
enable signal for external CODEC B
Programmable as positive (reset default) or negative
pulse.
Cologne
Chip
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