HFC-S+ Cologne Chip AG, HFC-S+ Datasheet - Page 66

• Manufacturer Part Number: HFC-S+
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C
10.2
Figure 13: Clock synchronisation in TE-mode
The C4IO clock is adjusted in the 31th time slot at the GCI/IOM bus twice for one half clock cycle. This
can be reduced to one adjustment of a half clock cycle. This is useful if another HFC-S, HFC-SP or HFC-
S+ is connected as slave in NT mode to the GCI/IOM2 bus.
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Clock synchronisation in TE-mode
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Cologne
Chip