HFC-S+ Cologne Chip AG, HFC-S+ Datasheet - Page 47

• Manufacturer Part Number: HFC-S+
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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Name
STATUS
Reading the STATUS register clears no bit.
Addr.
1Ch
Bits
0
1
2
3
4
5
6
7
r/w Function
r
r
r
r
r
r
r
r
BUSY/NOBUSY status
'1' the HFC-S+ is BUSY after initialising Reset FIFO,
'0' the HFC-S+ is not busy, all accesses are allowed
processing/non processing status
'1' the HFC-S+ is in processing phase (every 125µs)
'0' the HFC-S+ is not in processing phase
processing/non processing transition interrupt status
'1' The HFC-S+ has finished internal processing phase (every
unused, '0'
timer status
'0' timer not elapsed
'1' timer elapsed
TE/NT state machine interrupt state
'1' state of state machine has changed
FRAME interrupt has occured (any data channel interrupt)
all masked D-channel and B-channel interrupts are "ored"
ANY interrupt
all masked interrupts are "ored"
increment F or change FIFO
125µs)
Cologne
Chip
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