HFC-S+ Cologne Chip AG, HFC-S+ Datasheet - Page 26

• Manufacturer Part Number: HFC-S+
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C
3.5
The HFC-S+ includes a timer with interrupt capability. The timer counts F0IO pulses. So the timer
counter is incremented every 125µs. It can be reset by bit 7 of of the CTMT register. Furthermore the
timer is reset at every HFC-S+ access when bit 5 of the CTMT register is set. Seven different timer
values can be selected.
3.6
(only available in processor mode)
The watchdog outputs of the HFC-S+ are activated if the timer interrupt bit is active (not reset by reading
INT_S1) and the timer elapses a second time.
The reset of the timer counter itself and the watchdog value can be programmed in the CTMT register. In
automatic reset mode the watchdog/timer is reset by every access to the HFC-S+.
"& _V '
Timer
Watchdog
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Cologne
Chip