HFC-SPCI Cologne Chip AG, HFC-SPCI Datasheet - Page 16

• Manufacturer Part Number: HFC-SPCI
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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Register Name
Interrupt Line
Interrupt Pin
Min_Gnt
Max_Lat
Cap_ID
Next Ptr
PMC
PMCSR
Default Value
7E21h
0000h
FFh
01h
00h
10h
01h
00h
Remarks
This register must be configured by configuration write.
INTA supported
Value can be read from EEPROM. Base address for
configuration write is FCh.
Value can be read from EEPROM. Base address for
configuration write is FCh.
Capability ID. 01h identifies the linked list item as PCI
Power Management registers.
Power Management Capabilities. See also PCI Bus
Power Management Interface Specification. This
register's value can be read from EEPROM. Base
address for configuration write is E0h.
PME# can be asserted from D0, D1, D2 and D3
Device specific initialisation is required.
The HFC-S PCI does not require PCI-clock to generate
PME# (if S/T change state is selected).
This function complies with the PCI Power
Management Spec. Version 1.0.
Bits
15
14..9
8
7..2
1..0
There are no next items in the linked list.
Power Management Control/Status
Function
PME_Status - This bit is set when the function
would normally assert the PME# signal
independent of the state of the PME_En bit.
Writing a '1' to this bit will clear it and cause
the function to stop asserting a PME# (if
enabled).
Writing a '0' has no effect.
fixed to '0'
PME_En - A '1' enables the function to assert
PME#.
When '0', PME# assertion is disabled.
fixed to '0'
PowerState - This 2-bit field is used both to
determine the current power state of a function
and to set the function into a new power state.
00b - D0
01b - D1
10b - D2
11b - D3
All States except D0 disable HFC-S PCI master
accesses.
hot
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hot
.