HFC-SPCI Cologne Chip AG, HFC-SPCI Datasheet - Page 17

• Manufacturer Part Number: HFC-SPCI
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

Table 2: PCI configuration registers' initial values
Unimplemented registers return all 0's when read.
3.2
If the HFC-S PCI is used in memory mapped mode all register can directly be accessed by adding their
CIP address to the configured Memory Base Address.
In I/O address mapped mode the HFC-S PCI occupies 8 bytes in the I/O address space. Byte 0 is for data
read/write, byte 4 for register selection. The AUX-port address is selected by byte 3, AUX-port data is
read/written by byte 1.
Figure 3: HFC-S PCI in I/O address mapped mode
Figure 4: HFC-S PCI in memory address mapped mode
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Register Name
32K Memory Window
Base Address
(MWBA)
Internal HFC-S PCI register description
Default Value
0000h
Remarks
Bits[31:15] are r/w by configuration accesses.
The 32K Memory Window is for HFC-S PCI internal
use and for the B- and D-channel FIFOs. This register
must be written by a "DWORD Config Write" to enable
the HFC-S PCI to operate in master mode.
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