HFC-SPCI Cologne Chip AG, HFC-SPCI Datasheet - Page 23

• Manufacturer Part Number: HFC-SPCI
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

Because the HFC-S PCI is limited to the 32K Memory Window data in different regions of the host PC
can not be overwritten even if counter and pointer values are handled in a wrong way.
3.4.1
For each FIFO one F1 and one F2 counter is available. The counters are located at the following offsets
to the Memory Window Base Address (MWBA) in the Memory Window (MW).
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FIFO
B1-transmit
B1-receive
B2-transmit
B2-receive
D-transmit
D-receive
*
The counter state 0200h of the Z-counters follows counter state 1FFFh in the B-channel FIFOs.
The counter state 000h of the Z-counters follows counter state 1FFh in the D-channel FIFOs.
The counter state 00h of the F-counters follows counter state 1Fh in the B-channel FIFOs.
The counter state 10h of the F-counters follows counter state 1Fh in the D-channel FIFOs.
important!
These counters are handled by the HFC-S PCI automatically and must not be written by software.
FIFO counters location in Memory Window
Counter
F2
F1
F2
F1
F2
F1
F1
F1
F2
F1
F2
F2
*)
*)
*)
*)
*)
*)
Offset to Memory Window
Base Address
20A0h
20A1h
60A0h
60A1h
2080h
2081h
6080h
6081h
2180h
2181h
6180h
6181h
Counter Size
in Bytes
1
1
1
1
1
1
1
1
1
1
1
1
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