HFC-SPCI Cologne Chip AG, HFC-SPCI Datasheet - Page 47

• Manufacturer Part Number: HFC-SPCI
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

6.3
Timing diagram 1: GCI/IOM2 timing
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SYMBOL
t
t
t
t
t
t
t
t
t
C4P
C4H
C4L
C2P
C2H
F0iS
F0iH
F0iW
SToD
*)
GCI/IOM2 timing
F0IO starts one C4IO clock earlier if bit 3 in MST_MODE register is set. If this bit is set
F0IO is also awaited one C4IO clock cycle earlier.
Clock C4IO period (4.096 MHz)
Clock C4IO High Width
Clock C4IO Low Width
Clock C2O Period
Clock C2O High Width
F0IO Setup Time
F0IO Hold Time
F0IO Width
STIO1 Delay Level 1 Output
CHARACTERISTICS
243.9 ns
487.8 ns
110 ns
110 ns
220 ns
200 ns
MIN.
50 ns
50 ns
20 ns
244.4 ns
488.8 ns
134 ns
134 ns
268 ns
150 ns
300 ns
125 ns
150 ns
MAX
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