HFC-SPCI Cologne Chip AG, HFC-SPCI Datasheet - Page 22

• Manufacturer Part Number: HFC-SPCI
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

3.4
All FIFOs are located in the 32K Memory Window (MW) in host PC's memory.
There are 6 FIFOs with 6 HDLC-Controllers handled by the HFC-S PCI. The HDLC circuits are located
on the S/T device side of the HFC-S PCI. So always plain data is stored in the FIFO. Zero insertion and
deletion is done in HDLC mode:
– if the data goes to the S/T or GCI/IOM device in send FIFOs and
– when the HDLC data comes from the S/T device or GCI/IOM2 bus in receive operation.
There are a send and a receive FIFO for each of the two B-channels and for the D-channel.
The FIFOs are realized as ring buffers in the 32K Memory Window in host PC's memory. To control
them there are some counters.
Z1: FIFO input counter
Z2: FIFO output counter
Each counter points to a byte position in the Memory Window. This is an offset to the 32K Memory
Window Base Address in the configuration space. On a FIFO input operation Z1 is incremented. On an
output operation Z2 is incremented.
After every pulse on the F0IO signal two HDLC-bytes are written into the S/T interface (FIFOs No. 0
and 2) and two HDLC-bytes are read from the S/T interface (FIFOs No. 1 and 3).
D-channel data is handled in a similar way but only 2 bits are processed.
If Z1 = Z2 the FIFO is empty.
Additionally there are two counters F1 and F2 for every FIFO channel (5Bit for B-channel, 4Bit for D-
channel). They count the HDLC-frames in the FIFOs and form a ring buffer as Z1 and Z2 do, too.
F1 is incremented when a complete frame has been received and stored in the FIFO. F2 is incremented
when a complete frame has been read from the FIFO.
If F1 = F2 there is no complete frame in the FIFO.
When the RESET line is active or software reset is active Z1, Z2, F1 and F2 are all initialized to all 1s.
All Zx and Fx counters are also stored in the Memory Window. So it is easy to read and write the
counters by simple host memory accesses.
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*
Instead of the S/T interface also GCI/IOM2 bus is selectable for each B-channel (see CONNECT
register).
important!
FIFOs
B-channel D-channel
13 Bit
13 Bit
9 Bit
9 Bit
6URbeQbi !)))