WM8253SCDS/V Wolfson Microelectronics Ltd., WM8253SCDS/V Datasheet - Page 12

• Manufacturer Part Number: WM8253SCDS/V
• Description: Specifications: Manufacturer: Wolfson Microelectronics ; Product Category: ADC (A/D Converters) ; RoHS: Details ; Number of Converters: 1 ; Number of ADC Inputs: 1 ; Conversion Rate: 6 MSPs ; Resolution: 16 bit ; Input Type: Voltage ; Interface
• Manufacturer: Wolfson Microelectronics Ltd.

WM8253
CDS/NON-CDS PROCESSING
OFFSET ADJUST AND PROGRAMMABLE GAIN
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For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel
common mode noise. For CDS operation, the video level is processed with respect to the video reset
level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must
be set to 1 (default), this controls switch 2 (Figure 4) and causes the signal reference to come from
the video reset level. The time at which the reset level is sampled, by clock R
programming control bits CDSREF[1:0], as shown in Figure 6.
Figure 6 Reset Sample and Clamp Timing
For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed
with respect to the voltage on pin VRLC/VBIAS, generated internally or externally as described above.
The VRLC/VBIAS pin is sampled by R
The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset
DAC to compensate for offsets and then amplified by an 8-bit PGA. The gain and offset can be set for
each of three colours by writing to control bits DACx[7:0] and PGAx[7:0] (where x can be R, G or B).
In colour line-by-line mode the gain and offset coefficients that are applied to the PGA and offset DAC
can be multiplexed by control of the INTM[1:0] bits as shown in Table 1.
Table 1 Offset DAC and PGA Register Control
The gain characteristic of the WM8253 PGA is shown in Figure 7. Figure 8 shows the maximum input
voltage (at VINP) that can be gained up to match the ADC full-scale input range (2.0V).
INTM[1:0]
R
R
R
R
S
S
S
S
00
01
10
11
/CL (CDSREF = 00)
/CL (CDSREF = 01)
/CL (CDSREF = 10)
/CL (CDSREF = 11)
Red offset and gain registers are applied to offset DAC and PGA
(DACR[7:0] and PGAR[7:0])
Green offset and gain registers applied to offset DAC and PGA
(DACG[7:0] and PGAG[7:0])
Blue offset and gain registers applied to offset DAC and PGA
(DACB[7:0] and PGAB[7:0])
Reserved.
MCLK
VSMP
VS
s
at the same time as V
DESCRIPTION
s
samples the video level in this mode.
PD, Rev 4.1, August 2011
s
/CL, is adjustable by
Production Data
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