WM8253SCDS/V Wolfson Microelectronics Ltd., WM8253SCDS/V Datasheet - Page 13

• Manufacturer Part Number: WM8253SCDS/V
• Description: Specifications: Manufacturer: Wolfson Microelectronics ; Product Category: ADC (A/D Converters) ; RoHS: Details ; Number of Converters: 1 ; Number of ADC Inputs: 1 ; Conversion Rate: 6 MSPs ; Resolution: 16 bit ; Input Type: Voltage ; Interface
• Manufacturer: Wolfson Microelectronics Ltd.

WM8253
ADC INPUT BLACK LEVEL ADJUST
OVERALL SIGNAL FLOW SUMMARY
w
Figure 7 PGA Gain Characteristic
9
8
7
6
5
4
3
2
1
0
0
Gain re gis te r value (PGA[7:0])
64
128
The output from the PGA should be offset to match the full-scale range of the ADC (V
negative-going input video signals, a black level (zero differential) output from the PGA should be
offset to the top of the ADC range by setting register bits PGAFS[1:0]=10. For positive going input
signal the black level should be offset to the bottom of the ADC range by setting PGAFS[1:0]=11.
Bipolar input video is accommodated by setting PGAFS[1:0]=00 or PGAFS[1:0]=01 (zero differential
input voltage gives mid-range ADC output).
Figure 9 represents the processing of the video signal through the WM8253.
Figure 9 Overall Signal Flow
The INPUT SAMPLING BLOCK produces an effective input voltage V
difference between the input video level V
difference between the input video level V
set via the RLC DAC.
The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the
black level of the input signal towards 0V, producing V
The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range,
outputting voltage V
The ADC BLOCK then converts the analogue signal, V
The digital output is then inverted, if required, through the OUTPUT INVERT BLOCK to produce D
V
V
V
VRLCEXT=1
IN
RESET
VRLC
CDS = 0
192
CDS = 1
DAC
RLC
SAMPLING
VRLCEXT=0
BLOCK
INPUT
+
V
3
RLCSTEP
.
256
-
V
*RLCV[3:0] + V
1
OFFSET DAC
BLOCK
+ +
Offset
DAC
A = 0.78+(PGA[7:0]*7.57)/255
V
260mV*(DAC[7:0]-127.5)/127.5
Figure 8 Peak Input Voltage to Match ADC Full-scale Range
2
RLCBOT
BLOCK
PGA
X
PGA gain
IN
IN
and the voltage on the VRLC/VBIAS pin, V
and the input reset level V
V
3
analog
2.5
1.5
0.5
3
2
1
0
0
2
.
3
+65535 if PGAFS[1:0]=10
+32767 if PGAFS[1:0]=0x
, to a 16-bit unsigned digital output, D
+0
x (65535/V
if PGAFS[1:0]=11
ADC BLOCK
Gain re gis te r value (PGA[7:0])
64
FS
V
V
V
CDS, VRLCEXT,RLCV[3:0], DAC[7:0],
PGA[7:0], PGAFS[1:0] and INVOP are set
by programming internal control registers.
CDS=1 for CDS, 0 for non-CDS
)
IN
RESET
VRLC
is VINP voltage sampled on video sample
RESET
is voltage applied to VRLC pin
is VINP sampled during reset clamp
128
PD, Rev 4.1, August 2011
D
digital
. For non-CDS this is the
1
1
. For CDS, this is the
D2 = D1 if INVOP = 0
D2 =65535-D1 if INVOP = 1
OUTPUT
INVERT
BLOCK
192
Production Data
FS
VRLC
= 2.0V). For
, optionally
D
OP[3:0]
1
2
.
256
2.
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