WM8253SCDS/V Wolfson Microelectronics Ltd., WM8253SCDS/V Datasheet - Page 16

• Manufacturer Part Number: WM8253SCDS/V
• Description: Specifications: Manufacturer: Wolfson Microelectronics ; Product Category: ADC (A/D Converters) ; RoHS: Details ; Number of Converters: 1 ; Number of ADC Inputs: 1 ; Conversion Rate: 6 MSPs ; Resolution: 16 bit ; Input Type: Voltage ; Interface
• Manufacturer: Wolfson Microelectronics Ltd.

WM8253
CONTROL INTERFACE
TIMING REQUIREMENTS
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The internal control registers are programmable via the serial digital control interface. The register
contents can be read back via the serial interface on pin OP[3]/SDO.
It is recommended that a software reset is carried out after the power-up sequence, before writing to
any other register. This ensures that all registers are set to their default values (as shown in Table 4).
SERIAL INTERFACE: REGISTER WRITE
Figure 11 shows register writing in serial mode. Three pins, SCK, SDI and SEN are used. A six-bit
address (a5, 0, a3, a2, a1, a0) is clocked in through SDI, MSB first, followed by an eight-bit data word
(b7, b6, b5, b4, b3, b2, b1, b0), also MSB first. Each bit is latched on the rising edge of SCK. When
the data has been shifted into the device, a pulse is applied to SEN to transfer the data to the
appropriate internal register. Note all valid registers have address bit a4 equal to 0 in write mode.
Figure 11 Serial Interface Register Write
A software reset is carried out by writing to Address “000100” with any value of data, (i.e. Data Word
= XXXXXXXX.
SERIAL INTERFACE: REGISTER READ-BACK
Figure 12 shows register read-back in serial mode. Read-back is initiated by writing to the serial bus
as described above but with address bit a4 set to 1, followed by an 8-bit dummy data word. Writing
address (a5, 1, a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4, d3, d2, d1, d0) of
corresponding register (a5, 0, a3, a2, a1, a0) to be output MSB first on pin SDO (on the falling edge of
SCK). Note that pin SDO is shared with an output pin, OP[3], so no data can be read when reading
from a register. The next word may be read in to SDI while the previous word is still being output on
SDO.
Figure 12 Serial Interface Register Read-back
To use this device a master clock (MCLK) of up to 36MHz and a per-pixel synchronisation clock
(VSMP) of up to 6MHz are required. These clocks drive a timing control block, which produces
internal signals to control the sampling of the video signal. MCLK to VSMP ratios and maximum
sample rates for the various modes are shown in Table 3.
SDO
SCK
SEN
SCK
SEN
SDI
SDI
a5 1 a3 a2 a1 a0 x
a5
Address
0
Address
a3
a2
a1
x
Data Word
a0
x
x
b7
x
x
b6
x
b5
x
Data Word
b4
b3
d7 d6 d5 d4 d3 d2 d1 d0
b2
Output Data Word
PD, Rev 4.1, August 2011
b1
b0
Production Data
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