WM8253SCDS/V Wolfson Microelectronics Ltd., WM8253SCDS/V Datasheet - Page 23

• Manufacturer Part Number: WM8253SCDS/V
• Description: Specifications: Manufacturer: Wolfson Microelectronics ; Product Category: ADC (A/D Converters) ; RoHS: Details ; Number of Converters: 1 ; Number of ADC Inputs: 1 ; Conversion Rate: 6 MSPs ; Resolution: 16 bit ; Input Type: Voltage ; Interface
• Manufacturer: Wolfson Microelectronics Ltd.

WM8253
Table 5 Register Control Bits
w
Setup
Register 5
Setup
Register 6
Offset DAC
(Red)
Offset DAC
(Green)
Offset DAC
(Blue)
Offset DAC
(RGB)
PGA gain
(Red)
PGA gain
(Green)
PGA gain
(Blue)
PGA gain
(RGB)
REGISTER
BIT
3:1
7:5
2:1
4:3
7:5
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
NO
0
4
0
OPDLY[1:0]
POSNNEG
VSMPDET
DACR[7:0]
DACG[7:0]
DACB[7:0]
PGAR[7:0]
PGAG[7:0]
PGAB[7:0]
VDEL[2:0]
Reserved
Reserved
Reserved
Reserved
DAC[7:0]
PGA[7:0]
NAME(S)
BIT
DEFAULT
10000000
10000000
10000000
00000000
00000000
00000000
000
000
000
11
10
0
0
0
0 = Normal operation, signal on VSMP input pin is applied directly to
Timing Control block.
1 = Programmable VSMP detect circuit is enabled. An internal
synchronisation pulse is generated from signal applied to VSMP input pin
and is applied to Timing Control block.
When VSMPDET = 0 these bits have no effect.
When VSMPDET = 1 these bits set a programmable delay from the
detected edge of the signal applied to the VSMP pin. The internally
generated pulse is delayed by VDEL MCLK periods from the detected
edge.
See Figure 13, Internal VSMP Pulses Generated for details.
When VSMPDET = 0 this bit has no effect.
When VSMPDET = 1 this bit controls whether positive or negative edges
are detected:
0 = Negative edge on VSMP pin is detected and used to generate internal
timing pulse.
1 = Positive edge on VSMP pin is detected and used to generate internal
timing pulse.
See Figure 13 for further details.
Must be set to Zero
Must be set to Zero
Must be set to One
Programmable adjust on the output propagation time (t
00 = 8ns
01 = 12ns
10 = 14ns
11 = not valid
Must be set to zero
Red channel offset DAC value. Used under control of the INTM[1:0] control
bits.
Green channel offset DAC value. Used under control of the INTM[1:0]
control bits.
Blue channel offset DAC value. Used under control of the INTM[1:0]
control bits.
A write to this register location causes the red, green and blue offset DAC
registers to be overwritten by the new value
Determines the gain of the red channel PGA according to the equation:
Red channel PGA gain = [0.78+(PGAR[7:0]*7.57)/255]. Used under control
of the INTM[1:0] control bits.
Determines the gain of the green channel PGA according to the equation:
Green channel PGA gain = [0.78+(PGAG[7:0]*7.57)/255]. Used under
control of the INTM[1:0] control bits.
Determines the gain of the blue channel PGA according to the equation:
Blue channel PGA gain = [0.78+(PGAB[7:0]*7.57)/255]. Used under control
of the INTM[1:0] control bits.
A write to this register location causes the red, green and blue PGA gain
registers to be overwritten by the new value
DESCRIPTION
PD, Rev 4.1, August 2011
PD
)
Production Data
23