AT91FR40161 ATMEL Corporation, AT91FR40161 Datasheet - Page 18

• Manufacturer Part Number: AT91FR40161
• Description: The AT91FR40161 Features 136 K Bytes of On-chip SRAM, 2M Bytes of Flash, an External Bus Interface, a 3-channel Timer/Counter, 2 ...
• Manufacturer: ATMEL Corporation

EBI: External Bus
Interface
External Memory
Mapping
18
AT91X40 Series
The EBI generates the signals that control the access to the external memory or periph-
eral devices. The EBI is fully-programmable and can address up to 64M bytes. It has
eight chip selects and a 24-bit address bus, the upper four bits of which are multiplexed
with a chip select.
The 16-bit data bus can be configured to interface with 8- or 16-bit external devices.
Separate read and write control signals allow for direct memory and peripheral
interfacing.
The EBI supports different access protocols allowing single-clock cycle memory
accesses.
The main features are:
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The “EBI User Interface” is described on page 45.
The memory map associates the internal 32-bit address space with the external 24-bit
address bus.
The memory map is defined by programming the base address and page size of the
external memories (see “EBI User Interface” registers EBI_CSR0 to EBI_CSR7). Note
that A0 - A23 is only significant for 8-bit memory; A1 - A23 is used for 16-bit memory.
If the physical memory device is smaller than the programmed page size, it wraps
around and appears to be repeated within the page. The EBI correctly handles any valid
access to the memory device within the page (see Figure 6).
In the event of an access request to an address outside any programmed page, an
Abort signal is generated. Two types of Abort are possible: instruction prefetch abort
and data abort. The corresponding exception vector addresses are respectively
0x0000000C and 0x00000010. It is up to the system programmer to program the error
handling routine to use in case of an Abort (see the ARM7TDMI datasheet for further
information).
If two chip selects are defined as having the same base address, an access to the over-
lapping address space asserts both NCS lines. The Chip Select Register with the
smaller number defines the characteristics of the external access and the behavior of
the control signals.
External memory mapping
Up to 8 chip select lines
8- or 16-bit data bus
Byte write or byte select lines
Remap of boot memory
Two different read protocols
Programmable wait state generation
External wait request
Programmable data float time
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