AT91FR40161 ATMEL Corporation, AT91FR40161 Datasheet - Page 29

• Manufacturer Part Number: AT91FR40161
• Description: The AT91FR40161 Features 136 K Bytes of On-chip SRAM, 2M Bytes of Flash, an External Bus Interface, a 3-channel Timer/Counter, 2 ...
• Manufacturer: ATMEL Corporation

Wait States
Standard Wait States
1354D–ATARM–08/02
Figure 17. Data Hold Time
In early read protocol the data can remain valid longer than in standard read protocol
due to the additional wait cycle which follows a write access.
The EBI can automatically insert wait states. The different types of wait states are listed
below:
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•
•
•
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Each chip select can be programmed to insert one or more wait states during an access
on the corresponding device. This is done by setting the WSE field in the corresponding
EBI_CSR. The number of cycles to insert is programmed in the NWS field in the same
register.
Below is the correspondence between the number of standard wait states programmed
and the number of cycles during which the NWE pulse is held low:
For each additional wait state programmed, an additional cycle is added.
Standard wait states
Data float wait states
External wait states
Chip select change wait states
Early read wait states (see “Read Protocols” )
0 wait states1/2 cycle
1 wait state1 cycle
Data Output
ADDR
NWE
MCK
AT91X40 Series
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