AT94K ATMEL Corporation, AT94K Datasheet - Page 26

• Manufacturer Part Number: AT94K
• Description: 5K - 40K Gates of At40k FPGA with 8-bit Microcontroller, up to 36K Bytes of SRAM and On-chip JTAG ICE
• Manufacturer: ATMEL Corporation

B Side
26
AT94K Series FPSLIC
Table 5. AVR Data Decode for SRAM 0:17 (16K8)
The B side is not partitioned; the FPGA (and AVR debug mode) views the memory space as
36 x 8 Kbytes.
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Table 6. Summary Table for AVR and FPGA SRAM Addressing
SRAM
00
01
02
03
04
(1)
(1)
(1)
The B side is accessed by the FPGA/Configuration Logic.
The B side is accessed by the AVR with ST and LD instructions in DBG mode for code
self-modify.
To activate the debug mode and allow the AVR to access the program code space (with
ST – see Figure 21 – and LD – see Figure 22 – instructions), the DBG bit (bit 1) of the
SFTCR $3A ($5A) register has to be set. When this bit is set, SCR36 and SCR37 are
ignored – you can overwrite anything in the AVR program memory.
The FPGA memory access interface should be disabled while in debug mode. This is to
ensure that there is no contention between the FPGA address and data signals and the
AVR-generated address and data signals. To ensure the AVR has control over the “B
side” memory interface, the FMXOR bit (bit 3) of the SFTCR $3A ($5A) register should be
used in conjunction with the SCR63 system control register bit.
The FMXOR bit is XORed with the System Control Register’s Enable FPGA SRAM Inter-
face bit (SCR63). The behavior when this bit is set to 1 is dependent on how the SCR was
initialized. If the Enable FPGA SRAM Interface bit (SCR63) in the SCR is 0, the FMXOR
bit enables the FPGA SRAM Interface when set to 1. If the Enable FPGA SRAM Interface
bit in the SCR is 1, the FMXOR bit disables the FPGA SRAM Interface when set to 1. Dur-
ing AVR reset, the FMXOR bit is cleared by the hardware.
Even though the FPGA (and AVR debug mode) views the memory space as
36 x 8 Kbytes, an awareness of the 2K x 8 partitions (or SRAM labels) is required if Frame
(and AVR debug mode) read/writes are to be meaningful to the AVR.
AVR data to FPGA addressing is 1:1 mapping.
AVR program to FPGA addressing requires 16-bit to 8-bit mapping and an understanding
of the partitions in Table 6.
Address Range
$07FF – $0000
$0FFF – $0800
$17FF – $1000
$1FFF – $1800
$27FF – $2000
$2FFF – $2800
$37FF – $3000
$3FFF – $3800
FPGA and AVR DBG
Address Range
$0000 - $07FF
$0800 - $0FFF
$1000 - $17FF
$1800 - $1FFF
$2000 - $27FF
SRAM
Address Range
$0000 - $07FF
$0800 - $0FFF
$1000 - $17FF
$1800 - $1FFF
$2000 - $27FF
00
01
02
03
04
05
06
07
AVR Data
Comments
AVR Data Read/Write
AVR Data Read/Write
CR41:40 = 11,10,01
CR41:40 = 11,10
CR41:40 = 11
AVR PC Address Range
$3800 - $3FFF (LS Byte)
$3800 - $3FFF (MS Byte)
$3000 - $37FF (LS Byte)
Rev. 1138F–FPSLI–06/02