AT94K ATMEL Corporation, AT94K Datasheet - Page 84

• Manufacturer Part Number: AT94K
• Description: 5K - 40K Gates of At40k FPGA with 8-bit Microcontroller, up to 36K Bytes of SRAM and On-chip JTAG ICE
• Manufacturer: ATMEL Corporation

Boundary-scan
Description Language
Files
84
AT94K Series FPSLIC
Table 20. Bit EXTEST and SAMPLE_PRELOAD
Boundary-Scan Description Language (BSDL) files describe Boundary-Scan capable devices
in a standard format used by automated test-generation software. The order and function of
bits in the Boundary-Scan data register are included in this description. A BSDL file for AT94K
Family is available.
Enable Clock - TOSC 1
Enable Output - SDA
Enable Output - SCL
Clock Out/In - SCL
Clock In - TOSC 1
Data Out/In - SDA
AVR Reset
Bit Type
EXTEST
Observe only. Capture-DR grabs
signal from pad.
1 = clock disabled. Capture-DR
grabs clock enable from the AVR.
Observe only. Capture-DR grabs
signal from pad.
1 = drive “0”
0 = drive disabled, bus pull-up
Capture-DR grabs output enable
scan latch.
Observe only. Capture-DR grabs
signal from pad.
1 = drive “0”
0 = drive disabled, bus pull-up
Capture-DR grabs output enable
scan latch.
Internal, observe only.
Capture-DR grabs internal AVR
reset signal.
SAMPLE_PRELOAD
Capture-DR grabs signal from
pad if clock is enabled, “1” if
disabled.
Capture-DR grabs enable from
the AVR.
Capture-DR grabs signal from
pad.
Capture-DR grabs output enable
from the AVR.
Capture-DR grabs signal from
pad.
Capture-DR grabs output enable
from the AVR.
Capture-DR grabs internal AVR
reset signal.
Rev. 1138F–FPSLI–06/02