MCIMX25 Motorola Semiconductor Products, MCIMX25 Datasheet - Page 54

• Manufacturer Part Number: MCIMX25
• Manufacturer: Motorola Semiconductor Products

1
2
3
4
5
3.6.6
The EMI module includes the enhanced SDRAM/LPDDR memory controller (ESDCTL), NAND Flash
controller (NFC), and wireless external interface module (WEIM). The following subsections give timing
information for these submodules.
3.6.6.1
3.6.6.1.1
The following diagrams and tables specify the timings related to the SDRAMC module which interfaces
SDRAM.
54
The output SCLK transition time is tested with 25 pF drive.
T
T
T
T
sclk
wait
per
ipg
t10
t12
t13
t14
t11
ID
t5’
t6’
t7’
t4
t5
t6
t7
t8
t9
= CSPI main clock IPG_CLOCK period
= CSPI reference baud rate clock period (PERCLK2)
= CSPI clock period
= Wait time, as specified in the sample period control register
CSPI SCLK transition time
SSn output pulse width
SSn input pulse width
SSn output asserted to first SCLK edge (SS output setup
time)
SSn input asserted to first SCLK edge (SS input setup
time)
CSPI master: Last SCLK edge to SSn negated (SS
output hold time)
CSPI slave: Last SCLK edge to SSn negated (SS input
hold time)
CSPI master: CSPI1_RDY low to SSn asserted
(CSPI1_RDY setup time)
CSPI master: SSn negated to CSPI1_RDY low
Output data setup time
Output data hold time
Input data setup time
Input data hold time
Pause between data word
External Memory Interface (EMI) Timing
ESDCTL Electrical Specifications
SDRAM Memory Controller
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 2
Parameter Description
Table 39. CSPI Interface Timing Parameters (continued)
Symbol
t
t
t
t
t
t
Sdatao
Hdatao
t
t
t
Sdatai
Hdatai
t
t
t
pause
Wsso
t
Hsso
Wssi
Ssso
t
Hssi
Srdy
Hrdy
Sssi
pr
1
(t
t
2T
t
clkoL
clkoL
clkiL
t
clkiL
Minimum
sclk
T
ipg
3T
2T
2T
T
or t
or t
T
or t
T
2
2.6
30
per
ipg
or t
per
0
0
0
sclk
sclk
+ 0.5
+T
per
clkiH
clkoH
clkoH
5
4
clkiH
wait
) –
or
3
or
Freescale Semiconductor
Maximum
5T
8.5
—
—
—
—
—
—
—
—
—
—
—
—
per
Units
ns
—
—
—
—
—
ns
—
ns
—
—
ns
ns
ns